Mobility Degradation Analysis for La2O3 nMOSFET

Abstract

nMOSFET with various thicknesses of the La 2 O 3 layer and the SiO 2 interfacial layer (IL) were fabricated. We discussed mobility degradation caused by fixed charge and trapped charge at the La 2 O 3 /SiO 2 interface. IntroductionThe ultrathin gate dielectric has emerged as one of the most difficult challenges for future device scaling. According to the International Technology Roadmap of Semiconductors 2005 (ITRS2005), progress in scaling silicon oxynitride dielectric layer below 1 nm thickness (in equivalent oxide thickness, EOT) is considered impracticable because of high leakage current [1]. High dielectric constant materials (high-κ) is needed as early as in year 2008 for the 57 nm 1 / 2 pitch generation [1]. For this reason, much effort is currently underway on high-κ gate dielectrics.Hf-based family of high-κ gate dielectrics has been extensively studied during the past few years and is expected to be used starting year 2008. On the other hand, Group III or rare earth oxides (REOs), especially Lanthanum oxide (La 2 O 3 ) and Y 2 O 3 , are promising candidates to replace Hf-based gate dielectrics as the future gate dielectric. Detailed analyses of La 2 O 3 on interface structure by X-ray photoelectron spectroscopy (XPS) [2-3], conduction mechanisms [4][5], annealing effects [6-7] and promising electrical characteristics of MOSFETs [8-9] were reported.However, the effective mobility of high-κ gate dielectric MOSFETs is found to be significantly lower than the universal curve [10]. Furthermore, mobility degradation mechanism is still not completely clarified. In this paper, by changing the SiO 2 interfacial layer (IL) thickness [11], we studied the effect of fixed and trapped charge at La 2 O 3 /SiO 2 interface on mobility degradation. Charge pumping technique was used to evaluate the interface trap of this system. ExperimentsUltrathin La 2 O 3 films (EOT 1.1 nm and 2 nm) were deposited on thermal SiO 2 interfacial layers (IL) (0.9-2 nm) by electron-beam evaporation in a molecular-beamepitaxy (MBE) system. The chamber pressure and temperature during the deposition were 10 -7 Pa and 250 o C, respectively. The ex-situ post deposition anneal (PDA) was ECS Transactions, 2 (1) 329-338 (2006) 10.1149/1.2193905, copyright The Electrochemical Society 329 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 128.6.235.18 Downloaded on 2015-06-04 to IP 330conducted in the rapid thermal annealing (RTA) chamber with 1.2 l/min flow rate at 300 o C in either N 2 or O 2 ambient for 10 minutes before the Al gate electrode evaporation using bell-jar type evaporator at 10 -5 Pa. The gas lines and RTA chamber were carefully purged to minimize contamination of existing gases and particles prior to annealing. To avoid possible contamination on La 2 O 3 film and moisture absorption, the exposure time before Al gate evaporation was less than 1 hour. Gate length and width of the nMOSFET were 10 and 57 µm, respectively. Figure 1 outlines major fabrication steps...

Memristive device with highly continuous conduction modulation and its underlying physical mechanism for electronic synapse application

“…Schottky-type contacts are formed at Hf x Zr 1−x O 2 /Pt and Ta 2 O 5−x /TiN interfaces in accordance with the energy band diagram of the TTHZOP structure in Fig. 8a [55,56]. When a positive voltage is applied to the top electrode for electroforming operation, the Vos with positive charges will move to the bottom electrode, therefore, the distribution of Vos is changed.…”