Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

Jazaeri, Farzan; Barbut, Lucian; Sallese, J.-M.

doi:10.1109/ted.2013.2261073

Cited by 46 publications

(14 citation statements)

References 9 publications

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“…Relations (9) and (11) are the same as in [3], which justifies why the total charge per unit length in the silicon NWQ SC can be calculated from a JL DG model provided the parameter transformations proposed in Table I are done. The total charge in the NW expressed per unit lengthQ SC becomes…”

Section: B Accounting For the Gate Capacitancementioning

confidence: 96%

“…Therefore, it comes out that this approach is suitable to predict charges and currents in JL NW, and that the introduction of the effective semiconductor dielectric constant is found to be a simple and still reliable approximation to simulate thick and/or highly doped JL NW, which might not work properly for circuits applications due to design constrains [10], [11].…”

Section: Simulationsmentioning

confidence: 99%

See 1 more Smart Citation

A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs

Sallèse

Jazaeri

Barbut

et al. 2013

IEEE Trans. Electron Devices

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In this paper, we evidence the link between the planar and cylindrical junctionless field effect transistors (JL-FETs) from the electrostatics and current point of view. In particular, we show that an approximate solution of the Poisson-Boltzmann equation for JL nanowires can be mapped on the planar doublegate topology generating only negligible mismatch, meaning that both devices can share the same core model as far as long channels are considered. These preliminary results are a first step toward a unification of compact models for JL-FETs.Index Terms-Double gate (DG), enhancement mode, field effect transistor (FET), junctionless, modeling, nanowires (NWs).

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Section: B Accounting For the Gate Capacitancementioning

confidence: 96%

Section: Simulationsmentioning

confidence: 99%

A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs

Sallèse

Jazaeri

Barbut

et al. 2013

IEEE Trans. Electron Devices

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“…To extend the scalability of CMOS technology in sub nanometer regime, short channel effects (SCEs) such as large drain induced barrier lowering (DIBL), increased leakage currents, poor sub-threshold swing (SS) and threshold voltage roll off are the major challenges [1][2][3]. Researchers have been working on different structures through these years and have come up with devices with improved performances.…”

Section: Introductionmentioning

confidence: 99%

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

Roy

Gupta

Rai

2015

Microelectronics Journal

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“…In literatures [7][8][9][10][11], a plethora of analytical models of DG junctionless MOSFETs considering SCEs have been reported. These reported models have not incorporated the quantum mechanical effects for channel lengths less than 10 nm.…”

Section: Introductionmentioning

confidence: 99%

“…These reported models have not incorporated the quantum mechanical effects for channel lengths less than 10 nm. Most recently Jazaeri et al [7] has reported a model of long channel DG junctionless MOSFET to estimate the surface potential, critical point of mobile charge density, on-off current ratio etc. Besides Sallese et al [8] reported a charge based model of DG junctionless MOSFET to express analytical model of mobile charge density, threshold voltage, ON current etc.…”

Section: Introductionmentioning

confidence: 99%

Modeling of characteristic parameters for nano-scale junctionless double gate MOSFET considering quantum mechanical effect

Chanda¹,

De²,

Sarkar

2014

J Comput Electron

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This paper analytically models the characteristics parameters of nano-scale junctionless double gate MOSFETs under quantum confinement, as junctionless transistors gain advantages over their junction based counterparts recently. The models explicitly show how the device parameters like silicon channel thickness, oxide thickness, channel length etc. affect the characteristic parameters like surface potential, threshold voltage etc. when quantum mechanical effects dominate. We also study the effect of temperature on electron populations on sub-band energy levels. Variable quasi Fermi energy level is considered in this paper to increase the accuracy of the proposed models. Threshold voltage roll-off and drain induced barrier lowering are also analyzed to increase the efficacy of the models. These analytical models, valid from accumulation to depletion regimes, are validated and verified with the data obtained from Schrödinger-Poisson solver model of Technology Computer Aided Design. Simplicity of the proposed models give easy way to understand, analyze, and design Double Gate Junctionless transistors comprehensively.

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Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

Cited by 46 publications

References 9 publications

A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs

A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

Modeling of characteristic parameters for nano-scale junctionless double gate MOSFET considering quantum mechanical effect

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