Modeling and observing the jitter in ring oscillators implemented in FPGAs

Valtchanov, Boyan; Aubert, Alain; Bernard, Florent; Fischer, Viktor

doi:10.1109/ddecs.2008.4538777

Cited by 55 publications

(35 citation statements)

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“…Here we present a simple approach, introduced in [16], we call the counter method, to measure Q and ν inside the device. For i = 1, 2, the output signal of O i increments counter C i .…”

Section: The Counter Methodsmentioning

confidence: 99%

“…Following [16], it is important to distinguish the local component of the jitter, which is the entropy source of the TRNG, from the global deterministic noises, which can be manipulated from outside the device. But even the local component of the jitter is made of a combination of different types of noise with different statistical properties (see [14, p. 23]).…”

Section: ])mentioning

confidence: 99%

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Towards an Oscillator Based TRNG with a Certified Entropy Rate

Lubicz¹,

Bochard

2015

IEEE Trans. Comput.

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Abstract-We describe a practical and efficient method to determine the entropy rate of a TRNG based on free running oscillators that does not require outputting and analyzing the clock signals with external equipment. Rather it relies on very simple computations that can be embedded in any logic device such as FPGA or ASIC. The method can be used for the calibration of an oscillator based TRNG or for on-line certification of its entropy rate. Our approach, which is inspired by the coherent sampling method, works under the general assumption that the period jitter is small compared to the period of the generated clock signal. We show that, in this case, it is possible to measure the relative phase between clocks of two oscillators with far higher precision than the time resolution given by the period of any internal clock signal. We use this observation to recover, under some reasonable heuristics, the distribution of the random walk component of the jitter, from which it is possible to compute a lower bound of the entropy rate of the TRNG. Our method was thoroughly tested in simulations and in hardware. At the end of the paper, we draw some conclusions and make recommendations for a reliable implementation of TRNGs in cryptographic applications.

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“…Here we present a simple approach, introduced in [16], we call the counter method, to measure Q and ν inside the device. For i = 1, 2, the output signal of O i increments counter C i .…”

Section: The Counter Methodsmentioning

confidence: 99%

Section: ])mentioning

confidence: 99%

Towards an Oscillator Based TRNG with a Certified Entropy Rate

Lubicz¹,

Bochard

2015

IEEE Trans. Comput.

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“…In real circuit this factor is very important and cannot be ignored [36]. Moreover, propagation delays in all circuit paths and gates vary in time, because of shot noise, thermal noise and supply voltage instability [27], [39]. Having regards to this phenomenon the equation (1) must be submitted as…”

Section: A Jitter Produced By Ring Oscillators As a Source Of Randommentioning

confidence: 99%

“…is an accumulated jitter during previous half period of signal with frequency of f H and k delay elements [27]. It can be divided into deterministic factor and nondeterministic…”

Section: A Jitter Produced By Ring Oscillators As a Source Of Randommentioning

confidence: 99%

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Producing Random Bits with Delay-Line-Based Ring Oscillators

Jessa¹,

Matuszewski²

2013

International Journal of Electronics and Telecommunications

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Abstract-One of the sources of randomness for a random bit generator (RBG) is jitter present in rectangular signals produced by ring oscillators (ROs). This paper presents a novel approach for the design of delays used in these oscillators. We suggest using delay elements made on carry4 primitives instead of series of inverters or latches considered in the literature. It enables the construction of many high frequency ring oscillators with different nominal frequencies in the same field programmable gate array (FPGA). To assess the unpredictability of bits produced by RO-based RBG, the restarts mechanism, proposed in earlier papers, was used. The output sequences pass all NIST 800-22 statistical tests for smaller number of ring oscillators than the constructions described in the literature. Due to the number of ROs with different nominal frequencies and the method of construction of carry4 primitives, it is expected that the proposed RBG is more robust to cryptographic attacks than RBGs using inverters or latches as delay element.

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An Evaluation Procedure for Comparing Clock Jitter Measurement Methods

Garay

Bernard

Fischer

et al. 2023

Lecture Notes in Computer Science

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Modeling and observing the jitter in ring oscillators implemented in FPGAs

Cited by 55 publications

References 1 publication

Towards an Oscillator Based TRNG with a Certified Entropy Rate

Towards an Oscillator Based TRNG with a Certified Entropy Rate

Producing Random Bits with Delay-Line-Based Ring Oscillators

An Evaluation Procedure for Comparing Clock Jitter Measurement Methods

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