Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design

Saikia, Jyotishman; Yin, Shihui; Cherupally, Sai Kiran; Zhang, Bo; Meng, Jian; Seok, Mingoo; Seo, Jae-sun

doi:10.23919/date51398.2021.9473973

Cited by 13 publications

(7 citation statements)

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“…The input/weight quantization in IMC-SRAM modeling was used to evaluate the network accuracy. For simulation, the comparator offset sampling and the quantization of partial sum in IMC-SRAM modeling were used to evaluate the network accuracy. In addition, we assumed that there is no impact of V TH variation since ISPP can minimize the distribution of V TH .…”

Section: Resultsmentioning

confidence: 99%

“…To investigate the effect of signed weights in the CNN, we evaluated the network accuracy on the CIFAR-10 dataset using the VGG-8 network. The input/weight quantization in IMC-SRAM modeling 55 was used to evaluate the network accuracy. For simulation, the comparator offset sampling and the quantization of partial sum in IMC-SRAM modeling 55 were used to evaluate the network accuracy.…”

Section: Mac Operation For Signed Weight Computation Via the Fefet-pi...mentioning

confidence: 99%

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Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Kim

et al. 2022

ACS Appl. Mater. Interfaces

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Ferroelectric field-effect transistors (FeFETs) have attracted enormous attention for low-power and high-density nonvolatile memory devices in processing-inmemory (PIM). However, their small memory window (MW) and limited endurance severely degrade the area efficiency and reliability of PIM devices. Herein, we overcome such challenges using key approaches covering from the material to the device and array architecture. High ferroelectricity was successfully demonstrated considering the thermodynamics and kinetics, even in a relatively thick (≥30 nm) ferroelectric material that was unexplored so far. Moreover, we employed a metal−ferroelectric−metal− insulator−semiconductor architecture that enabled desirable voltage division between the ferroelectric and the metal−oxide−semiconductor FET, leading to a large MW (∼11 V), fast operation speed (<20 ns), and high endurance (∼10 11 cycles) characteristics. Subsequently, reliable and energy-efficient multiply-and-accumulation (MAC) operations were verified using a fabricated FeFET-PIM array. Furthermore, a system-level simulation demonstrated the high energy efficiency of the FeFET-PIM array, which was attributed to charge-domain computing. Finally, the proposed signed weight MAC computation achieved high accuracy on the CIFAR-10 dataset using the VGG-8 network.

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Section: Resultsmentioning

confidence: 99%

Section: Mac Operation For Signed Weight Computation Via the Fefet-pi...mentioning

confidence: 99%

Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Kim

et al. 2022

ACS Appl. Mater. Interfaces

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“…In order to extract several parameters of IMC structures, a wide range of methods are presented in various works. Among these methods, some prior works [27][28][29] have introduced simulation software to estimate the mentioned parameters. These simulators primarily focus on the correct estimation of the DNN performance rather than simulation runtime.…”

Section: Related Workmentioning

confidence: 99%

“…In [29], a Python -based framework is introduced to correctly estimate the accuracy of a DNN structure. It is mentioned that the model can predict this by considering several design parameters such as an activated row, partial sum quantization configurations, and non-idealities of several blocks in IMC.…”

Section: Software Simulation For Estimation Of Imc Performancementioning

confidence: 99%

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An Energy Consumption Model for SRAM-Based In-Memory-Computing Architectures

Akgül,

Karalar

2024

Electronics

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In this paper, a mathematical model for obtaining energy consumption of IMC architectures is constructed. This model provides energy estimation based on the distribution of a specific dataset. In addition, the estimation reduces the required simulation time to create an energy consumption model of SRAM-based IMC architectures. To validate our model with realistic data, the energy consumption of IMC is compared by using NeuroSim V3.0 for the CIFAR-10 and MNIST-like datasets. Furthermore, an application is created with our model to select highest performing quantization mapping based upon the parameters of energy consumption and accuracy.

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