Modeling and test for parasitic resistance and capacitance defects in PCM

Abstract

Parasitic capacitance and resistance have much influence on the performance of the phase change memory (PCM). Based on SPICE circuit simulations, this paper investigates possible faults caused by the parasitic capacitance and resistance defects in stand-alone PCM cells. A realistic set of fault models are proposed and a test algorithm is proposed to test the faults.

A snake addressing scheme for phase change memory testing

“…Almost all of the reported traditional PCM test algorithms are March test algorithms with a traditional linear addressing scheme [4][5][6]. The proposed snake addressing mode is compared with linear addressing in Figure 4.…”

“…The presence of contaminants or other impurities in the active region of the phase change material may result in parasitic parallel conductive paths in the PCM cell. These resistive or capacitive parasitic effects lead to an incomplete program fault 0 (IPF0), weak transition fault 0 (WTF0), write 1 destructive fault (WDF1), or weak write 1 destructive fault (WWDF1), depending on the value of the parasitic resistance and capacitance [4][5][6]. A read recovery disturb (RRD) fault, which is caused by the non-equilibrium state in the newly programmed cell, may occur when a cell is read immediately after it has been programmed to the RESET state [7].…”

Rebooting Computing: The Challenges for Test and Reliability

“…Testing CIM as memory: CIM accelerator typically consists of a crossbar memristive devices where each device could be e.g., a RRAM, STT-MRAM or a PCM memory device. Although some test and design-for-testability (DfT) schemes for such memories have been developed [27]- [30], there are still many open questions. The most important one arises from the lack of good defect models for the memristive devices.…”

Testing Computation-in-Memory Architectures Based on Emerging Memories

“…Nevertheless, there is some published work on emerging memories (relying on memristive devices) upon which CIM architectures are based. Most of this work is based on modeling defects as linear resistors, injecting them in the memory netlist in order to perform circuit simulation and derive fault models, and thereafter test and design-fortestability (DfT) solutions [10][11][12][13][14][15][16]. However, recent work has demonstrated that using resistors to model defects in, for example, RRAM and STT-MRAM is not accurate enough due to the non-linearity of these devices [17,18].…”