Rebooting Computing: The Challenges for Test and Reliability

Abstract

Today's computer architectures and semiconductor technologies are facing major challenges making them incapable to deliver the required features (such as computer efficiency) for emerging applications. Alternative architectures are being under investigation in order to continue deliver sustainable benefits for the foreseeable future society at affordable cost. These architectures are not only changing the traditional computing paradigm (e.g., in terms of programming models, compilers, circuit design), but also setting up new challenges and directions on the way these architectures should be tested to guarantee the required quality and reliability levels. This paper highlights the major open questions regarding test and reliability of three emerging computing paradigms being approximate computing, computation-in-memory and neuromorphic computing.

Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies

“…This paper shows that performing learning directly on faulty hardware reduces the impact of faults on the network accuracy by an average of 15% and, in extreme cases, can reach up to 30%. Moreover, in [80], faults affecting the signal-to-spike conversion layer have the strongest impact on the network accuracy, with the synaptic stuck-at faults coming to a very close second. These faults strongly affect the learning process, which only exacerbates during inference.…”

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

“…At the manufacturing level, the reliability of an MRAM cell can be degraded by: 1) device parameter deviations due to errors of lithography or etching process; 2) thermal disturbance [38]; and 3) dielectric breakdown. These phenomena may lead to TMR fluctuation, endurance degradation, data disturbance, retention failure, and so on [49], [50], which, in turn, may lead to access errors during the MRAM operations.…”

Exploiting Approximate Computing for implementing Low Cost Fault Tolerance Mechanisms

“…1 INL -École Centrale de Lyon, France -Email: alberto.bosio@ec-lyon.fr 2 Instituto de Informatica, PGMicro -Universidade Federal do Rio Grande do Sul, Brazil -Email: gsrodrigues@inf.ufrgs.br 3 Computer Engineering Lab, Delft University of Technology, The Netherlands -Email: S.Hamdioui@tudelft.nl…”

“…However, today's computing architectures (mainly based on the CMOS technology) are facing major challenges making them unable to meet the requirements. Such challenges are: power wall, memory wall and Instruction Level Parallelism wall [1]- [3]. For example, the memory wall is due to the increasing gap between processor and memory speeds, which limits the data transfer time and leads to significant energy consumption during the data transfer varying from 70% up to 90% of the overall energy spent by the computing system [4].…”