Modeling chemically amplified resists for 193-nm lithography

Croffie, Ebo H.; Cheng, Mu Jeng; Neureuther, Andrew R.; Houlihan, Francis M.; Cirelli, Raymond A.; Sweeney, James R.; Dabbagh, G.; Watson, Patrick; Nalamasu, Omkaram; Rushkin, Ilya L.; Dimov, Ognian; Gabor, Allen H.

doi:10.1117/12.388300

Cited by 3 publications

(2 citation statements)

References 2 publications

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“…Resist modeling deals with resist processes such as initial acid generation, postexposure bake and development. Although full physical 3D resist models have been developed to simulate these processes [20][21][22], the computational cost is so high in both runtime and memory usage that they can only be used for small-scale lithography simulations. For full-chip applications the so-called compact 2D resist models are generally used instead.…”

Section: Resist Modelingmentioning

confidence: 99%

(Invited) Advanced Modeling for Full-Chip Low-k₁ Lithography Simulations

Liu¹

2013

ECS Trans.

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Full-chip computational lithography is an important technology that enables low-k1 patterning. Examples of its applications include optical proximity correction (OPC), source-mask optimization (SMO) and verifications. In these applications, lithography models are required to predict the printed patterns on the wafer. Therefore the model accuracy has a direct impact to the quality of the final result. Rigorous physical models are accurate but computationally expensive. Therefore simple approximate models are generally used in full-chip applications. As the k1-factor continues to shrink, the errors produced by these simple models become unacceptable. Advanced models with improved accuracy and reasonable speed are required for low-k1 applications. In this work we will discuss the issues with the existing full-chip models and the development of advanced models.

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Section: Resist Modelingmentioning

confidence: 99%

(Invited) Advanced Modeling for Full-Chip Low-k₁ Lithography Simulations

Liu¹

2013

ECS Trans.

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“…While 3D physical resist models have been available for many years [11][12][13]. They are computationally too expensive for full-chip applications and are therefore generally found only in small-scale lithography simulators.…”

Section: State Of the Artmentioning

confidence: 99%

A full-chip 3D computational lithography framework

Liu¹,

Zhang²,

Lan³

et al. 2012

SPIE Proceedings

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3D lithography simulations capable of modeling 3D effects in all lithographic processes are becoming critical in OPC and verification applications as semiconductor feature sizes continue to shrink. These effects include mask topography, resist profile and wafer topography. In this work we present an efficient computational framework for full-chip 3D lithography simulations. Since fast modeling of mask topography effects has been studied for many years and is a relatively mature area, we will only briefly review a full-chip 3D mask model, Tachyon M3D, to highlight the importance and modeling requirements for accurate prediction of best focus variations among different device features induced by mask topography. We will focus our discussions on a full-chip 3D resist model, Tachyon R3D, its derivation and simplification from a full physical resist model. The resulting model form is fully compatible with the existing 2D resist model with added capabilities for resist profile and top loss prediction. A benchmark against the full physical model will be presented as well. We will also describe the development of a full-chip 3D wafer topography model, Tachyon W3D, and the preliminary results against rigorous simulations.

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