Modeling of Dynamic Operation of T-RAM Cells

Abstract

This paper presents a comprehensive simulation analysis of the dynamic operation of T-RAM cells. The analysis addresses the evolution of cell electrostatics and of carrier concentrations and flows in the device when the gate voltage undergoes a fast low-to-high switch, as required by both read and write operations. The results clarify, first of all, the basic physics making holes in the p-base the physical element allowing information storage in the device. From this starting point, the working principles exploited for DRAM operation of the memory cell are then explained. Index Terms-Forward breakover, gated thyristors, nanoscale semiconductor devices, semiconductor device modeling, thyristor RAM (T-RAM).

On the Nature of the Memory Mechanism of Gated-Thyristor Dynamic-RAM Cells

“…From the carrier profiles in Fig. 3, contrary to the above conclusion ([3]- [6]), accumulation of holes is actually observed in the p-base, under the gate, for both memory states "1" (p ∼4.2x10 18 cm −3 ) and "0" (∼3.4x10 17 cm −3 ). This means that the physical memory mechanism cannot be the accumulation or depletion of holes in the base, under the gate, as claimed in [3]- [6].…”

“…The MOS gate provides capacitive coupling to the p-base of the TCCT, which enables switching speeds orders of magnitude faster than conventional thyristors [2]. A detailed investigation of the TRAM operation and design recently ([3]- [6]) concluded that "holes in the p-base under the gate represent the physical parameter determining the memory state of the cell" [5]: accumulation of holes for state "1", depletion of holes for state "0". The emphasis of these papers ([3]- [6]) was mainly on the process of the so called "dynamic sensing".…”

“…A detailed investigation of the TRAM operation and design recently ([3]- [6]) concluded that "holes in the p-base under the gate represent the physical parameter determining the memory state of the cell" [5]: accumulation of holes for state "1", depletion of holes for state "0". The emphasis of these papers ([3]- [6]) was mainly on the process of the so called "dynamic sensing". Thus the above conclusion was actually not based on a rigorous simulation of the carrier profiles in the memory HOLD (i.e., store) state.…”

Optically tunable feedback operation of silicon nanowire transistors

“…As the illumination intensity increases from 0 to 1.5 mW cm −2 , the latch-up and latch-down voltages shift from 2.95 to 1.79 V and 1.84 to 1.17 V, respectively. The latch-up (or latch-down) voltage can be modulated by gatecontrolled carrier injection in the field-effect diodes [25,26], gated thyristors [27,28], Z 2 -FETs [21,29], and FBFETs [22,23]. It is worth noting that, instead of gate control, the potential barriers can be tuned using illumination.…”

Steep switching characteristics of single-gated feedback field-effect transistors

“…Thus, the impact ionization model, which induces the abrupt current flow, was not considered in this work. This model is not one of the important factors that can affect the operation of FBFET or the device utilizing the same principle [18,19,26].…”