Modeling of monolithic lumped planar transformers up to 20 GHz

Abstract

A new method for characterization of nionolithic lumped planar transformers is proposed in this paper. A lumped low-order equivalent; model is derived from the physical layout using a new expression for the substrate loss. Two transformers are considered in detail, showing excellent agreement between simulation and ineasurement. sc1

Integrated RF Front-End in 0.13 ¿m CMOS for Automotive and Industrial Applications beyond 20 GHz

“…The classical double-balanced Gilbert type mixer [5] is considered as the best solution to combine acceptable gain, noise figure and linearity. To obviate the problems caused by the low supply voltage of 1.5 V for the 0.13 µm CMOS process, a fully differential integrated transformer [6] was inserted between the input transconductance stage and the switching pairs. Power supply is connected to the center tap of primary winding of the transformer while the center tap of secondary winding is grounded.…”

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“…The designs of the planar square transformers are based on a model described in [15] and are implemented as coupled inductors. The model in Fig.…”

A 24-Gb/s 27 ¿ 1 Pseudo Random Bit Sequence Generator IC in 0.13 ¿m Bulk CMOS

“…Equivalent circuit of the shunt peaking inductances. This inductance model including parasitics [13] is used for circuit simulation. Figure 6 shows the equivalent circuit [13] of the symmetric shunt peaking inductor used in circuit simulation.…”

“…This inductance model including parasitics [13] is used for circuit simulation. Figure 6 shows the equivalent circuit [13] of the symmetric shunt peaking inductor used in circuit simulation. The series resistance is denoted by R p , the interwinding capacitance is modeled by C F .…”