Modeling of Parasitic Fringing Capacitance in Multifin Trigate FinFETs

Lee, KwangWon; An, TaeYoon; Joo, Sanghoon; Kwon, Kee-Won; Kim, Soyoung

doi:10.1109/ted.2013.2252467

Cited by 30 publications

(10 citation statements)

References 6 publications

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“…In Trigate FETs, an additional selective etching step of the hard mask is involved in order to create the third gate on top of the channel. Although this third gate adds to process complexity, it also leads to some advantages like reduced fringe capacitances and additional transistor width [28][29][30].…”

Section: Introductionmentioning

confidence: 99%

FinFETs: From Devices to Architectures

Bhattacharya

Jha

2014

Advances in Electronics

164

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Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.

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Section: Introductionmentioning

confidence: 99%

FinFETs: From Devices to Architectures

Bhattacharya

Jha

2014

Advances in Electronics

164

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“…Although it is out of the scope of this paper, this approach can be generalized to other architectures such as nanowires [28], [29] or FinFET [30], [31]. Finally, this model is simple and efficient enough for implementation in the MASTAR platform.…”

Section: Discussionmentioning

confidence: 99%

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Hiblot

Rafhay

Bœuf

et al. 2015

IEEE Trans. Electron Devices

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In this paper, the main MOSFET parasitic capacitances of planar devices (i.e., bulk, Fully depleted silicon-on-insulator (FDSOI), and planar double gate) are computed using two successive conformal mapping transforms. First, the structure is mapped to the real axis of the complex plane, and then the second transform, deduced directly from the Schwarz-Christoffel theorem, reduces the capacitance to the trivial parallel electrodes case. This second step involves elliptic integrals, which provide a generic expression for all parasitic capacitances. This method is later compared against other models based on conformal mapping. Finally, the results are validated with finite-element method simulations of the inner and outer fringe capacitances in different architectures, including metallic contacts and raised and faceted junctions.Index Terms-CMOS, compact model, conformal mapping, electrostatic, elliptic integrals, Model for Assessment of CMOS Technologies and Roadmaps (MASTAR), MOSFET, parasitic capacitance, roadmap.

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“…For example, between the gate and the source there will be two sided capacitors other than the top and the bottom capacitors as shown in Figure 20 [24]. And the transistor which has multiple fins increases the parasitic resistance (from each fin) and adds interconnect capacitances between fins [24] [25]. Also, the fabrication process is complicated and more complex than planar technologies especially for the vertical etching, which gives more opportunities to have variations between the shapes and heights of the Fins [26] which causes a variation of the threshold voltage of each transistor [27] as shown in Figure 21.…”

Section: -Nm Intel's 3d Tri-gate Transistormentioning

confidence: 99%

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I

Mohsen¹,

Harb²,

Deltimple³

et al. 2017

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Nowadays, transistor technology is going toward the fully depleted architecture; the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers' applications.

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Modeling of Parasitic Fringing Capacitance in Multifin Trigate FinFETs

Cited by 30 publications

References 6 publications

FinFETs: From Devices to Architectures

FinFETs: From Devices to Architectures

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I

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