Modeling of Pattern Dependencies for Multi-Level Copper Chemical-Mechanical Polishing Processes

Tugbawa, Tamba; Park, Tae; Lee, Brian; Boning, Duane S.

doi:10.1557/proc-671-m4.3

Cited by 29 publications

(20 citation statements)

References 2 publications

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“…A statistical model 143 describing the interaction between pad asperities and wafer has also been proposed by Yu et al Yet another approach is to model abrasive particle, pad asperity, and wafer surface interactions incorporating wear mechanisms such as adhesive wear, abrasive wear, erosive wear, and corrosive wear to predict the variation of removal rates with applied pressure. [144][145][146] Boning et al 147,148 have developed an integrated contact mechanics and density-step-height model that views the CMP process as a chemically enhanced mechanical process. Contact mechanics is used to compute the local pressure at various points on a three-dimensional envelope function that captures the long-range topography at chip level.…”

Section: Models Based On Contact Mechanicsmentioning

confidence: 99%

Chemical Mechanical Planarization: Slurry Chemistry, Materials, and Mechanisms

Krishnan¹,

Nalaskowski²,

Cook³

2009

Chem. Rev.

409

271

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Mahadevaiyer Krishnan received his Ph.D. degree in Physical Chemistry/ Electrochemistry from Georgetown University under the direction of Prof. Robert de Levie. He was a postdoctoral fellow under Prof. A. J. Bard in the University of Texas at Austin. He joined the IBM T. J. Watson Research Center at Yorktown Heights in 1984 as a research scientist. Krishnan's research interests include interfacial electrochemistry, colloid and surface science, and semiconductor process development. He has been leading research and development as well as manufacturing implementation of CMP slurries and processes in IBM since 1994.

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Section: Models Based On Contact Mechanicsmentioning

confidence: 99%

Chemical Mechanical Planarization: Slurry Chemistry, Materials, and Mechanisms

Krishnan¹,

Nalaskowski²,

Cook³

2009

Chem. Rev.

409

271

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“…When considering a wafer with significant variations in pattern density, typical polishing processes yield dramatic variations in local removal rate. 2 As a result, determining local and global removal rates becomes difficult, especially when considering that little is known about the contact mechanisms at the pad-wafer interface. This limitation reduces the capability of accurately determining the actual pressure experienced by the structures on the wafer surface.…”

mentioning

confidence: 99%

Estimating the Effective Pressure on Patterned Wafers during STI CMP

Sorooshian

Borucki

Timon

et al. 2004

Electrochem. Solid-State Lett.

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Removal rate results obtained from a 150 mm Speedfam-IPEC 472 polisher, coupled with a proven removal rate model has allowed for the determination of effective pressure ͑i.e., the actual pressure exerted on the structures of a patterned wafer͒ during chemical mechanical planarization ͑CMP͒ of high-density plasma-filled shallow trench isolation ͑STI͒ wafers. Results showed that the ratio of derived effective pressure to applied wafer pressure was 2.2, 1.7, and 1.3 for 10, 50, and 90% density wafers, respectively. The relative consistency of these ratios indicates that the effective pressure experienced during polishing is not impacted by pattern density in a proportionate manner.It is critical to establish a problem-free approach for shallow trench isolation ͑STI͒ chemical mechanical planarization ͑CMP͒ because STI technology presents several advantages over the previous LOCOS ͑local oxidation of silicon͒ technology such as low junction capacitance, near zero-field encroachment, and exceptional latch-up immunity. 1 The general structure and property of materials used in STI technology has caused selectivity issues ͑i.e., oxide vs. nitride removal rates͒, nitride erosion, and trench oxide dishing. The aforementioned problems are generally associated with the overall material properties ͑i.e., Young's modulus͒ of the various STI layers, as well as variations of local removal rates resulting from the effects of patterned structures on the actual wafer pressure experienced during CMP.Patterned wafers pose uniformity problems due to inconsistent planarization times resulting from variations in die-level pattern density. For a set of identical CMP process conditions and wafers with no variations in pattern density ͑i.e., uniform and repeated patterns͒, more material is removed from a wafer with a lower pattern density than from one with a higher pattern density. When considering a wafer with significant variations in pattern density, typical polishing processes yield dramatic variations in local removal rate. 2 As a result, determining local and global removal rates becomes difficult, especially when considering that little is known about the contact mechanisms at the pad-wafer interface. This limitation reduces the capability of accurately determining the actual pressure experienced by the structures on the wafer surface.This study attempts to determine the effective pressure ͑i.e., the actual pressure exerted on the structures of a patterned wafer, also known as the envelop pressure͒ during STI CMP through a series of controlled temperature STI polishes. Using removal rate results in conjunction with a simplified Langmuir-Hinshelwood kinetics mechanism for material removal, this study derives the effective pressure experienced for STI wafers ranging in pattern densities of 10-90%. 3 ExperimentalPolishing.-All polishes were completed on a Speedfam-IPEC Avanti-472 polisher using 150 mm diameter wafers. The STI wafers used in the study had pattern densities of 10, 50, and 90% and exhibited no die-level pattern density va...

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“…On the other hand, for the integration of low-k dielectric materials, a move towards low-pressure CMP techniques and fixed abrasive polish pads is observed. For these techniques, the CMP planarization length is increased [14,15]. This will have a negative impact on CMP-induced signal strength variations.…”

Section: Future Workmentioning

confidence: 99%

Alignment robustness for 90 nm and 65 nm node through copper alignment mark integration optimization

Warrick¹,

Hinnen

Morton

et al. 2005

Optical Microlithography XVIII

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In this paper, methods for stacking ASML scribe lane alignment marks (SPM) and improving the mark performance at initial copper metal levels are discussed. The new mark designs and the theoretical reasons for mark design and/or integration change are presented. In previous joint publications between ASML and Freescale Semiconductor [1], improved overlay performance and alignment robustness for Back End Of Line (BEOL) layers by the application of stacked scribe lane marks (SPM) was presented.In this paper, further improvements are demonstrated through the use of optimized Versatile Scribe Lane Mark design (VSPM). With the application of stacked optimized VSPM-marks, the alignment signal strength of marks in the copper metal layer is increased compared to stacked SPM marks. The gains in signal strength stability, which is typical for stacked marks, as well as significantly reduced scribe lane usage, are also maintained. Through the placement of specially designed orthogonal scatter-bars in selected layers under the VSPM-marks, the alignment performance of initial inlaid metal layers is improved as well. The integration of these marks has been evaluated for the 90 nm and 65 nm technology nodes as part of a joint development program between the Crolles2 Alliance and ASML. A measured overlay improvement of ~10-15% was obtained by a strategy change from floating copper marks to stacked optimized VSPM marks.

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Modeling of Pattern Dependencies for Multi-Level Copper Chemical-Mechanical Polishing Processes

Cited by 29 publications

References 2 publications

Chemical Mechanical Planarization: Slurry Chemistry, Materials, and Mechanisms

Chemical Mechanical Planarization: Slurry Chemistry, Materials, and Mechanisms

Estimating the Effective Pressure on Patterned Wafers during STI CMP

Alignment robustness for 90 nm and 65 nm node through copper alignment mark integration optimization

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