Modeling of simultaneous switching noise in high speed systems

Chun, Sungjun; Swaminathan, Madhavan; Smith, Larry; Srinivasan, J.; Zhang, Jin; Iyer, M.K.

doi:10.1109/6040.928747

Cited by 104 publications

(3 citation statements)

References 10 publications

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“…A transient current injected in power distribution network (PDN) can cause a significant amount of simultaneous switching noise (SSN) which is a major source of jitter, skew and radiated emission problems [8]. The amount of the SSN is linearly proportional to the total loop inductance of the entire PDN.…”

Section: Low-inductance Connection Of Power Distribution Networkmentioning

confidence: 99%

Edge plating for building large arrays and low-inductance board-to-board connection

Park

Kam

2018

IEICE Electron. Express

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Section: Low-inductance Connection Of Power Distribution Networkmentioning

confidence: 99%

Edge plating for building large arrays and low-inductance board-to-board connection

Park

Kam

2018

IEICE Electron. Express

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“…In particular, parallel-plate noise is a serious problem because it significantly affects system performance. Moreover, it is induced by a parallel-plate waveguide that is frequently adopted for power delivery networks in high-speed PCBs [2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

A Dual-Perforation Electromagnetic Bandgap Structure for Parallel-Plate Noise Suppression in Thin and Low-Cost Printed Circuit Boards

Kim

2019

Electronics

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In this study, we propose and analyze a dual-perforation (DP) technique to improve an electromagnetic bandgap (EBG) structure in thin and low-cost printed circuit boards (PCBs). The proposed DP–EBG structure includes a power plane with a square aperture and a patch with an L-shape slot that overcomes efficiently the problems resulting from the low-inductance and the characteristic impedance of the EBG structure developed for parallel-plate noise suppression in thin PCBs. The effects of the proposed dual-perforation technique on the stopband characteristics and unit cell size are analyzed using an analytical dispersion method and full-wave simulations. The closed-form expressions for the main design parameters of the proposed DP–EBG structure are extracted as a design guide. It is verified based on full-wave simulations and measurements that the DP technique is a cost-effective method that can be used to achieve a size reduction and a stopband extension of the EBG structure in thin PCBs. For the same unit cell size and low cut-off frequency, the DP–EBG structure increases the stopband bandwidth by up to 473% compared to an inductance-enhanced EBG structure. In addition, the unit cell size is substantially reduced by up to 94.2% compared to the metallo–dielectric EBG structure. The proposed DP–EBG technique achieves the wideband suppression of parallel plate noise and miniaturization of the EBG structure in thin and low-cost PCBs.

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“…Cosimulation of PDN and channel model requires long simulation time and often results in convergence issues (Chun et al, 2001). Furthermore, supply noise in the system strongly depends on the switching data pattern.…”

Section: Fig 1: Block Diagram Of Dllmentioning

confidence: 99%

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

O.¹

2012

Journal of Computer Science

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Problem statement:In any multimedia processor, controller may consume most of the onchip memory resources. The memory requirement is directly depends on algorithm shared by different blocks, so leads to failure in the system models. Approach: This study presents the implementation of DLL unit used for memory optimization. Various aspects of the underlying coarse lock detector are explored and modifications are made with software reference implementation. The whole system is implemented in 0.18 µm CMOS technology, where an input reference clock to an outgoing data clock monitors and true locking is initialized with 50% duty cycle correction. Results: From the measurement result of DLL operation, the output clock jitter is analyzed. Power consumption of DLL including large size output buffer is about few mW. Conclusion: The great challenge in this implementation is communication bandwidth, has brought to process variation and power state reduction techniques. In addition, inefficiency of computing capacity and simultaneous switching noise is reduced in the real time applications.

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Modeling of simultaneous switching noise in high speed systems

Cited by 104 publications

References 10 publications

Edge plating for building large arrays and low-inductance board-to-board connection

Edge plating for building large arrays and low-inductance board-to-board connection

A Dual-Perforation Electromagnetic Bandgap Structure for Parallel-Plate Noise Suppression in Thin and Low-Cost Printed Circuit Boards

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

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