Modeling statistical dopant fluctuations in MOS transistors

Stolk, P. A.; Widdershoven, F.; Klaassen, D.B.M.

doi:10.1109/16.711362

Cited by 378 publications

(163 citation statements)

References 24 publications

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“…Horstmann and co-workers [70] investigated global and local matching of sub-100 nm n-channel metal-oxide-semiconductor (NMOS) and p-channel metal-oxide-semiconductor (PMOS)-transistors and confirmed the area law proposed in [68]. The empirical analytical expression by Mizuno was generalized by Stolk et al [71] by taking into account the finite thickness of the inversion layer, the depth-distribution of the charge in the depletion layer and the influence of the source and drain impurity distributions. Numerical drift-diffusion and hydrodynamic simulations [72,73,74,75] have also confirmed the existence of the fluctuations in the threshold voltage in ultra-small devices.…”

Section: Discrete Impurity Effectsmentioning

confidence: 93%

Quantum and Coulomb Effects in Nano Devices

Vasileska¹,

Khan²,

Ahmed³

et al. 2011

Nano-Electronic Devices

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In state of the art devices, it is well known that quantum and Coulomb effects play significant role on the device operation. In this paper we demonstrate that a novel effective potential approach in conjunction with a Monte Carlo device simulation scheme can accurately capture the quantummechanical size quantization effects. We also demonstrate, via proper treatment of the short-range Coulomb interactions, that there will be significant variation in device design parameters for devices fabricated on the same chip due to the presence of unintentional dopant atoms at random locations within the channel.

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Section: Discrete Impurity Effectsmentioning

confidence: 93%

Quantum and Coulomb Effects in Nano Devices

Vasileska¹,

Khan²,

Ahmed³

et al. 2011

Nano-Electronic Devices

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“…However, all previous 3D simulation studies of random dopant fluctuation effects [11,15,20] do not take into account quantum effects. It is important to evaluate to what extent the quantum effects would affect the random dopant-induced threshold voltage fluctuation and lowering, and to what degree the threshold voltage lowering may compensate for the increase in the threshold voltage associated with inversion layer quantization [27].…”

Section: Simulation Approachmentioning

confidence: 99%

“…These architectures have additional benefits in terms of optimal threshold voltage control and improved mobility [19][20][21][22]. The undoped epitaxial layer thickness is restricted to approximately one-fifth of the effective channel length, due to short channel effects.…”

Section: Fluctuation Resistant Mosfet Architecturesmentioning

confidence: 99%

Statistical 3D ‘atomistic’ simulation of decanano MOSFETs

Asenov

Slavcheva

Brown

et al. 2000

Superlattices and Microstructures

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A 3D statistical 'atomistic' simulation technique has been developed to study the effect of the random dopant induced parameter fluctuations in aggressively scaled MOSFETs. Efficient implementation of the 'atomistic' simulation approach has been used to investigate the threshold voltage standard deviation and lowering in the case of uniformly doped MOSFETs, and in fluctuation-resistant architectures utilising epitaxial-layers and delta-doping. The effect of the random doping in the polysilicon gate on the threshold voltage fluctuations has also been thoroughly investigated. The influence of a single-charge trapping on the channel conductivity in decanano MOSFETs is studied in the 'atomistic' framework as well. Quantum effects are taken into consideration in our 'atomistic' simulations using the density gradient formalism.

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“…On-chip process parameter variations are classified into global variations and local variations [7]. The above adaptive techniques try to compensate for or make use of knowledge of the global component of the parameters based on measurements.…”

Section: Introductionmentioning

confidence: 99%

Device-Parameter Estimation through IDDQ Signatures

Shintani

Satō

2013

IEICE Trans. Inf. & Syst.

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SUMMARYWe propose a novel technique for the estimation of deviceparameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations.

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Modeling statistical dopant fluctuations in MOS transistors

Cited by 378 publications

References 24 publications

Quantum and Coulomb Effects in Nano Devices

Quantum and Coulomb Effects in Nano Devices

Statistical 3D ‘atomistic’ simulation of decanano MOSFETs

Device-Parameter Estimation through IDDQ Signatures

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