Modelling of thermal failure of metallic interconnects under electrostatic discharge transients

Amin, Karim; Fikry, W.; Sabry, Mohamed-Nabil; Ragai, Hani

doi:10.1049/el:20052032

Cited by 8 publications

(1 citation statement)

References 4 publications

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“…ESDs are transient discharges, which arise from human handling or contact with machines. Typical values for current and duration are 1 A and 200 ns [17]. The occuring energy can lead to thermal errors, which are categorized in two types: latent errors do not physicaly damage conducters but reduce the mean electromigration lifetime by a factor of 4.…”

Section: Physical Layermentioning

confidence: 99%

ARROW - A Generic Hardware Fault Injection Tool for NoCs

Birner

Handl

2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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TodaysNoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techniques and like the system itself, it has to be validated and tested. A vulnerable point of attack for faults in distribiuted systems like NoCs is certainly the interconnect. In this paper, we will give an overview about todays challenges in interconnect technology and potential resulting physical faults. Unfortunately, describing faults on the physical level is far too accurate and so it is necessary to abstract and to map all these faults to a logical level. In more complex systems, also the logical level may become too detailed. As a result, an even more abstract layer, which is defined as the functional level, has to be introduced. To be able to verify fault tolerance, an experiment based test approach like fault injection is necessary. Arrow is a generic hardware fault injection tool, written in the hardware description language VHDL, especially designed for digital fault injection on the interconnect of NoCs, making use of fault models from the logical level. 1

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Section: Physical Layermentioning

confidence: 99%

ARROW - A Generic Hardware Fault Injection Tool for NoCs

Birner

Handl

2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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Transient thermal analysis of global interconnects based on transmission lines

Shang

Mao

2012

2012 Asia-Pacific Symposium on Electromagnetic Compatibility

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In this paper, an efficient numerical method is proposed for transient thermal analysis of global interconnects. The thermal behaviour of global interconnects is modelled as two dimensional heat transfer. The horizontal heat conduction along the line is described by the differential form of one dimensional heat diffusion equation, and the vertical heat conduction from the line to the substrate is modelled by the corresponding thermal transmission lines with the input admittance reduced by one moment matching technique. Then finite difference method is adopted to solve the proposed heat diffusion equation and the transient thermal response of global interconnects can be obtained. Numerical results show that the proposed method is more efficient than thermal field solver based on finite element method, and more accurate than equivalent thermal circuit solutions, with accuracy above 98%. I. [NTRODUCTION Rapid technology scaling enables hundreds of millions of transistors to be densely packed into a single chip. Therefore, high temperature problems caused by huge heat dissipation seriously affect performance and reliability of integrated circuits [1]. Since the peak temperature often appear at the top of the chip, which deteriorates the interconnect performance by increasing the interconnect resistance. The signification of accurately estimating the thermal behaviours of interconnects increases rapidly.Until this date, numerous efforts have been made to estimate interconnects temperature distribution. Three dimensional (3�) thermal fields of interconnects can be accurately simulated with numerical methods, such as finite difference method (FOM) [2], finite element method (FEM) [3] and boundary element method (BEM) [4], etc. These methods require a large number of computational nodes, which lead to long computational time. To improve efficiency, various approaches were proposed, including analytical solutions [5][6] and equivalent thermal circuit solutions [7] [10], which trade lengthy computational time for reduced resolution and accuracy. The equivalent thermal resistance circuits in [7][8] neglect thermal capacitance and hence are suitable for fast analysis of the steady-state louie heating in interconnects. To allow for transient thermal analysis of interconnects, the equivalent thermal resistance-capacitance (RC) circuits were proposed in [9][[0]. However, the transmission line effect on transient thermal profile of global interconnects should be considered due to high thickness of insulator and long length of interconnects. In this paper, a FDM-based method is proposed for transient thermal analysis of global interconnects. One dimensional heat conduction equation along the line is derived with the vertical heat dissipation modelled as a thermal transmission line and simplified with one moment matching technique. Numerical results from the method are compared with those from FEM and the equivalent thermal RC circuit solution. It is shown that the proposed method is more accurate than the thermal RC circuit solut...

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An electrothermal model of interconnects based on a transmissionline network

Shao

Mao

2012

2012 Asia Pacific Microwave Conference Proceedings

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Modelling of thermal failure of metallic interconnects under electrostatic discharge transients

Cited by 8 publications

References 4 publications

ARROW - A Generic Hardware Fault Injection Tool for NoCs

ARROW - A Generic Hardware Fault Injection Tool for NoCs

Transient thermal analysis of global interconnects based on transmission lines

An electrothermal model of interconnects based on a transmissionline network

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