Modified scan architecture for an effective scan testing

Paramasivam, K.; Gunavathi, K.; Nirmalkumar, A.

doi:10.1109/tencon.2008.4766794

Cited by 2 publications

(2 citation statements)

References 14 publications

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“…While aforementioned gating methods mainly have tried to reduce the level of switching activity in the combinational part, a few schemes can be found in the literature that have concentrated on reducing the level of switching activity in scan cell. A modified scan element has been presented in [10] to reduce scan cell switching activity. architectures, respectively.…”

Section: Previous Workmentioning

confidence: 99%

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A Novel Scan Architecture for Low Power Scan-Based Testing

Naeini

Ooi

2015

VLSI Design

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Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17% total average power compared to conventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures.

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Section: Previous Workmentioning

confidence: 99%

“…We have improved the modified scan element [10] and named it gating scan cell. According to Figure 4, each gating scan cell consists of three main substructures: gating logic, we have utilized a transmission gate and an inverter to gate the scan output to the combinational logic.…”

Section: The Proposed Gating Scan Architecturementioning

confidence: 99%