Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories

Abdelhadi, Ameer; Lemieux, Guy; Shannon, Lesley

doi:10.1109/fpl.2018.00049

Cited by 13 publications

(8 citation statements)

References 5 publications

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“…If the implemented scale is required to expand, scalability‐friendly solutions can be considered. For example, the DDR or HBM‐based BCAM 26 can be used to implement the indirection table, and more resource‐efficient TCAM 27,28 can be used to implement the rule table. In the conditions above, we implement the design on Intel N3000, and the resource utilization is listed in Table 4.…”

Section: Methodsmentioning

confidence: 99%

FGLB: A fine‐grained hardware intra‐server load balancer based on 100 G FPGA SmartNIC

2022

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In today's data centers, workloads including multiple services and requests are processed in parallel within a server with many CPU cores. Therefore, meeting the intra-server load balancing is very important to improve the utilization of CPU resources in the data centers. However, the existing methods cannot well meet the intra-server load balancing in high-throughput scenarios. The software-based methods generally utilize CPU cores to parse and dispatch packets. They work well at low throughput, but they have high CPU overhead at high throughput, leading to packet loss and high latency issues. The hardware-based methods parse the packet and compute a hash over its metadata in hardware and perform load balancing in a coarse-grained manner based on the hash value. They have the ability to work at high throughput with the advantage of low overhead but are less well in balance effect and flexibility. We, therefore, propose an intra-server load balancer based on the reconfigurable hardware, FPGA, to meet the requirements for load balancing within servers in high-speed application scenarios. Our method improves the load-balancing gran-ularity of hardware-based method. It not only has high throughput but also has a good balance effect and flexibility. We implemented and evaluated our method on a 100 G FPGA SmartNIC. The evaluation result shows our method can reduce the load imbalance ratio by an order of magnitude when the distribution of flow size is uneven compared to the current widely used hardware-based method.

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Section: Methodsmentioning

confidence: 99%

FGLB: A fine‐grained hardware intra‐server load balancer based on 100 G FPGA SmartNIC

2022

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“…After offloading, all packet processing related to the rule table is taken over by the FPGA, which can prevent overuse of the CPU cores to perform the IP searching and packet processing. Since the resource consumption linked to hardware implementation of the LPM table is extremely relevant to the width of the table [46], we do not implement the entire LPM table with the maximum IP width-that is, 128 bits for IPv6. Dividing the entire LPM table into two smaller tables with widths of 32 and 128 bits makes the implementation of LPM more resource-efficient.…”

Section: Offloading Lpm-based Cached-rule Table For Ip Routing Accelerationmentioning

confidence: 99%

“…Hardware-implemented TCAMs are able to search the whole memory space for a specific value within a single clock cycle due to their ability to perform a massively parallel search. There are two main implementation approaches of TCAM, namely registers-based and RAM-based, and the RAM-based solution is more applicable for large-scale implementation[46]. RAM-based TCAM is always implemented using the transposition method.…”

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confidence: 99%

AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC

et al. 2021

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Software-defined networking (SDN) has attracted much attention since it was proposed. The architecture of the SDN data plane is also evolving. To support the flexibility of the data plane, the software implementation approach is adopted. The software data plane of SDN is commonly implemented on a commercial off-the-shelf (COTS) server, executing an entire processing logic on a commodity CPU. With sharp increases in network capacity, CPU-based packet processing is overwhelmed. However, completely implementing the data plane on hardware weakens the flexibility. Therefore, hybrid implementation where a hardware device is adopted as the accelerator is proposed to balance the performance and flexibility. We propose an FPGA SmartNIC-based reconfigurable accelerator to offload some of the operation-intensive packet processing functions from the software data plane to reconfigurable hardware, thus improving the overall data plane performance while retaining flexibility. The accelerated software data plane has a powerful line-rate packet processing capability and flexible programmability at 100 Gbps and higher throughput. We offloaded a cached-rule table to the proposed accelerator and tested its performance with 100 GbE traffic. Compared with the software implementation, the evaluation result shows that the throughput can achieve a 600% improvement when processing small packets and a 100% increase in large packet processing, and the latency can be reduced by about 20× and 100×, respectively, when processing small packets and large packets.

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“…Alternate approaches to TCAM include Z-TCAM, 17 Static Random Access Memory (SRAM)-based TCAM realization and indirect indexed TCAM. 18 However, most of these schemes are used to realize small-sized experimental TCAMs and do not seem to be suitable for practical deployments.…”

Section: Longest Prefix Matchingmentioning

confidence: 99%

A minimal resource high‐speed routing lookup mechanism for servers with NetFPGAs

Sankaran¹,

Sivalingam

2021

Trans Emerging Tel Tech

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This paper studies how high-performance computer servers, equipped with Field-Programmable Gate Arrays (FPGAs), can perform high-speed routing. In particular, routing table lookup is considered since it is a key packet processing bottleneck for future routers that need to operate at Petabits-per-second.The paper defines and evaluates three routing lookup schemes used by routers/switches, using Xilinx NetFPGA SUME programmable data plane hardware boards. Two existing schemes, namely IP address-based Longest Prefix Matching and Multi-Protocol Label Switching tag-based exact matching are implemented. In addition, the paper presents a new routing scheme called No Lookup Forwarding Scheme (NLFS) that does not use conventional lookup tables. The NLFS approach adds a custom routing tag that does not require any form of (forwarding) table lookup, and independent of the Binary/Ternary Content Associate Memory (CAM) capacity in the switch/router. The experimental results show that the NLFS scheme utilizes less FPGA resources, while reducing packet lookup latency by up to 18% against longest prefix match which is the de facto lookup mechanism used in switches. The key contribution of this work is that it enables the use of NetFPGAs to reduce CAM capacity requirements in switches/routers to help reduce memory costs. The proposed scheme has several use cases, including provision of on-demand increase of packet routing capacity in data center networks and support for Network Function Virtualization-based systems.

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Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories

Cited by 13 publications

References 5 publications

FGLB: A fine‐grained hardware intra‐server load balancer based on 100 G FPGA SmartNIC

FGLB: A fine‐grained hardware intra‐server load balancer based on 100 G FPGA SmartNIC

AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC

A minimal resource high‐speed routing lookup mechanism for servers with NetFPGAs

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