Monitoring and WCET analysis in COTS multi-core-SoC-based mixed-criticality systems

Nowotsch, Jan; Paulitsch, Michael; Henrichsen, Arne; Pongratz, Werner; Schacht, Andreas

doi:10.7873/date.2014.080

Cited by 11 publications

(10 citation statements)

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“…These analyses benefit from full knowledge of the internals of the memory controller, such as page policies, transaction scheduler and the DRAM command scheduler, and exploit this information to produce tight bounds. On the software side, servers with memory budgets, built into the operating system, have been proposed to limit the memory interference (Nowotsch et al 2014;Yun et al 2012;Behnam et al 2013;Yun et al 2013) from tasks executing on other cores, enabling it to be managed based on enforcement rather than characterization. Our work contrasts to these efforts in the sense that it considers both the software and hardware to be given with no interface or any other means to modify/re-configure it.…”

Section: Related Workmentioning

confidence: 99%

A framework for memory contention analysis in multi-core platforms

2015

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The last decade has witnessed a major shift towards the deployment of embedded applications on multi-core platforms. However, real-time applications have not been able to fully benefit from this transition, as the computational gains offered by multi-cores are often offset by performance degradation due to shared resources, such as main memory. To efficiently use multi-core platforms for real-time systems, it is hence essential to tightly bound the interference when accessing shared resources. Although there has been much recent work in this area, a remaining key problem is to address the diversity of memory arbiters in the analysis to make it applicable to a wide range of systems. This work handles diverse arbiters by proposing a general framework to compute the maximum interference caused by the shared memory bus and its impact on the execution time of the tasks running on the cores, considering different bus arbiters. Our novel approach clearly demarcates the arbiter-dependent and independent stages in the analysis of these upper bounds. The arbiter-dependent phase takes the arbiter and the task memory-traffic pattern as inputs and produces a model of the availability of the bus to a given task. Then, based on the availability of the bus, the arbiter-independent phase determines the worst-case request-release scenario that maximizes the interference experienced by the tasks due to the contention for the bus. We show that the framework addresses the diversity problem by applying B Dakshina Dasari 123 Real-Time Syst it to a memory bus shared by a fixed-priority arbiter, a time-division multiplexing (TDM) arbiter, and an unspecified work-conserving arbiter using applications from the MediaBench test suite. We also experimentally evaluate the quality of the analysis by comparison with a state-of-the-art TDM analysis approach and consistently showing a considerable reduction in maximum interference.

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Section: Related Workmentioning

confidence: 99%

A framework for memory contention analysis in multi-core platforms

2015

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“…The work in [18] proposed an analysis method to compute an inflated WCET due to the contention for access to main memory by leaving the fine grained arbitration to the hardware. This approach requires the knowledge of resource demand for each task in a quantified value such as the number of accesses.…”

Section: Predictable Access To Main Memorymentioning

confidence: 99%

Schedulability analysis of global memory-predictable scheduling

Alhammad

Pellizzoni

2014

Proceedings of the 14th International Conference on Embedded Software

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The use of multicore CPUs in real-time systems poses significant challenges in estimating their temporal behavior. A factor that has a large impact on this issue is the contention for access to main memory among multiple cores. To overcome this problem, an execution model called PREM has been previously introduced to co-schedule CPU execution and accesses to main memory without relying on hardware arbiters. In this paper, we provide a global schedulability analysis for this predictable execution model, and we prove its correctness. We also evaluate the effectiveness of the proposed solution with extensive simulations. The results show a significant advantage of the proposed solution when compared to contention execution in which tasks access main memory unpredictably.

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“…Nowotsch et al [29] propose a novel approach for integrating temporal partitioning and WCET analysis. Their proposed approach extends the existing single-core techniques with determining the maximum number of shared resource accesses per shared resource.…”

Section: B Resource Monitoringmentioning

confidence: 99%