Monitoring process-induced focus errors using high-resolution flatness metrology

Abstract

Reducing focus errors during optical lithography patterning is crucial for minimizing defects and for achieving the desired critical dimension uniformity (CDU). Factors that contribute to lithography defocus originate from both within and outside the exposure tools. Wafer geometry and topography have been shown to be a major contributor to the focus budget, but decoupling wafer issues from scanner tooling / chuck signatures is far from trivial. In this paper we will review how the use of flatness metrology in a 22nm manufacturing environment improved our ability to measure focus errors as well as enabled the decoupling of error between tooling and wafer sources. We will also review several examples of experimental datasets demonstrating how this wafer shape measurement technique has provided unique insight to the nature of topography based focus error, as well as provide a valuable learning mechanism for driving improvement in process cycles of learning.