Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

Abstract

We demonstrate monolithic 3D integration of logic and memory in arbitrary vertical stacking order with the ability to use conventional inter-layer vias to connect between any layers of the 3D IC. We experimentally show 4 vertically-stacked layers (logic layer followed by two memory layers followed by another logic layer), enabled by the integration of traditional silicon-FETs (on the bottom-most layer) with low-processing-temperature emerging nanotechnologies: metal-oxide resistive random-access memory (RRAM), and carbon nanotube-FETs (CNFETs). As a demonstration, we show a routing element of a switchbox for a field-programmable gate array (FPGA), with each component of the routing element (involving both logic and memory elements) on their own vertical layer. Introduction Monolithic Three-Dimensional IntegrationThree-dimensional (3D) integration is a promising technology option for improving the performance, energy efficiency, and footprint of electronic systems [1]. Today's 2.5D and 3D integration are achieved through chip-stacking, with multiple vertical circuit layers connected using Through-Silicon Vias (TSVs). Monolithic 3D integration, whereby each circuit layer is thin and is fabricated directly over the previous circuit layers on the same substrate, can use conventional inter-layer vias (ILVs) to connect between various layers. The use of conventional vias rather than TSVs allows for massive vertical interconnect density, potentially maximizing the benefits of 3D integrated circuits (ICs) [1]. Moreover, monolithic 3D integration of logic and memory can enable new architectures and potentially alleviate the logic-memory communication bottleneck [2,3].

Monolithic 3-D FPGAs

“…The yield of PMOS devices was not enough to demonstrate the functionality of a working three-layer 3-D FPGA, but individual functional devices were obtained at each layer. More recently, in 2014, Shulaker et al [87] built a 1T-2R-based switch element for FPGAs, with a CNFET as the selection transistor and RRAM devices for the programmable resistors. The component devices of the switch element were realized on different layers.…”

System design challenges for future consumer devices: From glass to Chromebooks

“…Today's mobile AP SOC with billions of transistors is as powerful as the mainframe server a few decades ago. As the CMOS semiconductor technology scaling slows down, we should be looking into new innovations in the 3D device fabrication [1] and package integration [2] to keep the Moore's law going.…”

Nano-engineered architectures for ultra-low power wireless body sensor nodes

“…Carbon nanotube field-effect transistors (CNFETs) naturally overcome this temperature barrier since all fabrication steps can be accomplished below 200°C. Systems that monolithically integrate RRAM and CNFETs (on top of silicon transistors) have already been experimentally demonstrated [Shulaker14].…”