Monolithically stackable hybrid FPGA

Abstract

-The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic architectures. The novel FPGA structure is based on the combination of CMOL (Cmos + MOLecular scale devices) FPGA circuits and recent improvements and generalization of the CMOL concept to allow multilayer crossbar integration, compatibility with state-of-the-art foundries, and a wide range of available memristive crosspoint devices. Preliminary results indicate that with no optimization and only conventional CMOS technology, the proposed circuits can be at least ten times denser (and potentially faster) than CMOS FPGAs with the same design rules and similar power density. The second part of this paper shows that this performance can be further improved using optimal MUX-based logic architecture.

Hybrid CMOS/nanodevice circuits for high throughput pattern matching applications

“…[17] for crossbar wire capacitance, f max ≈ p max F nano / (K C seg V 2 ) ≈ 100 MHz for F nano = 3 nm and F CMOS = 45 nm, and f max ≈ 1 GHz for F nano = 45 nm and F CMOS = 130 nm. The pattern matching throughputs per unit area, defined as N bits f max /A cell , corresponding to these two cases are 10 19 and 10 18 bits/s/cm 2 , respectively, which is much higher than any reported state-of-the art concepts.…”

“…far beyond resolution of conventional optical lithography. Finally, fabrication process for some devices does not involve high temperatures opening possibilities for monolithical back-end integration of multiple layers on CMOS substrate [16,19]. Even if crossbar wires are defined with optical lithography so that F nano = F CMOS , the effective footprint of the TCAM cell could be still very small, i.e.…”

“…The advantages of the proposed circuits are mainly due the following three features: (i) ultra-dense diodelike stackable TCAM memory cell; (ii) high communication bandwidth three dimensional hybrid CMOS/nanodevice circuitry enabled by area-distributed interface (called CMOL [15,16]); and (iii) modified CMOL FPGA circuit architecture [17][18][19] with low reconfiguration overhead. Let us now discuss more in detail these features.…”

“…with F nano = F CMOS , because it provides high accuracy of overlay alignment for all layers in the circuits. In this case, instead of implementing tilted crossbar, one can rotate the position of vias so that all metal lines satisfy Manhattan geometry [19].…”

Cell Mapping for Nanohybrid Circuit Architecture Using Genetic Algorithm

“…A typical nanohybrid circuit architecture developed by Likharev K K's group and named Cmos/nanowire/MOLecular hybrid (CMOL) [3] , has advantages to be memories [4][5] , field programmable gate array (FPGA) [6][7] and neuromorphic CrossNets [8] . However, the development of corresponding computer aided design (CAD) tools is far from demand.…”