Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation

Abstract

This paper describes a comparison of two Montgomery modular multiplication architectures: a systolic and a multiplexed. Both implementations target FPGA devices. The modular multiplication is employed in modular exponentiation processes, which are the most important operations of some public-key cryptographic algorithms, including the most popular of them, the RSA. The proposed systolic architecture presents a high-radix implementation with a one-dimensional array of Processing Elements. The multiplexed implementation is a new alternative and is composed of multiplier blocks in parallel with the new simplified Processing Elements, and it provides a pipelined operation mode. We compare thetime×areaefficiency for both architectures as well as an RSA application. The systolic implementation can run the 1024 bits RSA decryption process in just 3.23 ms, and the multiplexed architecture executes the same operation in 4.36 ms, but the second approach saves up to 28% of logical resources. These results are competitive with the state-of-the-art performance.

High-Performance Elliptic Curve Cryptography by Using the CIOS Method for Modular Multiplication

“…In order to implement the modular Montgomery multiplication for fixed security level, we must choose the most suitable architecture. The results presented in this work are compared with the previous work [4,5,18,19] in the Table 3. We can notice that our results are better than [19] considering every point of comparison i.e.…”

“…the number of slice and the number of clock cycles. Considering the number of slices, we recall that [19] used an external memory to optimize the number of slices used by their algorithms. Considering the comparison with [18], our design requires less slices and can ran at a better frequency, without considering the huge progress in the number of clock cycles.…”

“…It's one of the most suitable algorithm for performing modular multiplications in hardware and software implementations. The efficient implementation of the Montgomery Modular Multiplication (MMM) in hardware was considered by many authors [3,6,7,18,19,23]. There is a variety of ways to perform the MMM, considering if multiplication and reduction are separated or integrated.…”

“…There is a variety of ways to perform the MMM, considering if multiplication and reduction are separated or integrated. A systolic array architecture [12,24] is one possibility for the implementation of the Montgomery algorithm in hardware, with a design both parallel and pipelined [3,18,19,20,23]. A similar work [20] has been done for binary fields (field characteristic is a power of 2) without having to deal with carry propagation as a consequence.…”

Hardware-software co-design of elliptic curve digital signature algorithm over binary fields

“…Wordwise Montgomery implementation provides significant speed advantages at the cost of higher resource utilization wherein the input operands can be processed in m words of k bits each. Therefore, the choice of the word size has to be optimum so as to maintain a reasonable trade-off between speed and resource utilization [12].…”