Localization of nodes in wireless sensor networks without the use of GPS is important for applications such as military surveillance, environmental monitoring, robotics, domotics, animal tracking, and many others. Low cost and energy efficient sensors require methods that compute their position using indirect information such as RSSI (Received Signal Strength Indicator). This work presents an artificial neural networks (ANNs) approach to localization in wireless sensor networks through the adjustment of the ANNs structures using Genetic Algorithms. A population of feedforward ANNs containing their structure in a genetic code is evolved during 20 generations. Each individual is evaluated through the training of the artificial neural network and further calculation of its root mean square error for all the testing set. The RSSI measurements were used as the artificial neural networks inputs to localize the nodes. The approach was tested using the MATLAB-based Probabilistic Wireless Network Simulator (Prowler) to collect the artificial neural networks input data, under simulated static indoor network environment of 26x26 meters with 8 anchor nodes, i.e., nodes with awareness of their positions. The MATLAB's genetic algorithms and artificial neural networks toolboxes were used. Results using the best artificial neural network structure found after optimization had a root mean square error of 0.41 meters, a maximum error of 1.07 meters and a minimum error of 0.014 meters.

This paper presents the design of a low-power high-CMRR CMOS instrumentation amplifier (IA) aimed for biomedical applications. The amplifier fundamentals were initially presented followed by its main building blocks. Simulation and experimental results were presented and discussed. The IA circuit was designed in AMIS 1.5 µm technology and manufactured through the MOSIS Service. The measured gain,CMRR and power consumption were 65dB, 120dB and 100uW respectively

This paper describes a comparison of two Montgomery modular multiplication architectures: a systolic and a multiplexed. Both implementations target FPGA devices. The modular multiplication is employed in modular exponentiation processes, which are the most important operations of some public-key cryptographic algorithms, including the most popular of them, the RSA. The proposed systolic architecture presents a high-radix implementation with a one-dimensional array of Processing Elements. The multiplexed implementation is a new alternative and is composed of multiplier blocks in parallel with the new simplified Processing Elements, and it provides a pipelined operation mode. We compare thetime×areaefficiency for both architectures as well as an RSA application. The systolic implementation can run the 1024 bits RSA decryption process in just 3.23 ms, and the multiplexed architecture executes the same operation in 4.36 ms, but the second approach saves up to 28% of logical resources. These results are competitive with the state-of-the-art performance.

This paper presents a proposal of a Gigabit UDP/IP network stack in FPGA, which is the stack of the widely used in VoIP and Video-conference applications. This network node implements the Network, Transport and Link Layer of a traditional stack. This architecture is integrated and developed using Xilinx ISE tool and synthesized to a Spartan-3E FPGA. We show architecture details, timing and area results of a practical prototyping. Also, we compare our prototype and results with other works in terms of area (Xilinx slices), speed (MHz), maximum Ethernet frame length (bytes) and maximum Ethernet speed (Mbps). Comparing to these works our architecture obtained a intermediate solution in area and is the best implementation in terms of speed (MHz).Index Terms-UDP/IP, network stack, FPGA.

No abstract