MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy

Abstract

Given the diverse range of application characteristics that chip multiprocessors (CMPs) need to cater to, a "onecache-topology-fits-all" design philosophy will clearly be inadequate. In this paper, we propose MorphCache, a Reconfigurable Adaptive Multi-level Cache hierarchy. MorphCache dynamically tunes a multi-level cache topology in a CMP to allow significantly different cache topologies to exist on the same architecture. Starting from per-core L2 and L3 cache slices as the basic design point, MorphCache alters the cache topology dynamically by merging or splitting cache slices and modifying the accessibility of different cache slice groups to different cores in a CMP. We evaluated MorphCache on a 16 core CMP on a full system simulator and found that it significantly improves both average throughput and harmonic mean of speedups of diverse multithreaded and multiprogrammed workloads. Specifically, our results show that MorphCache improves throughput of the multiprogrammed mixes by 29.9% over a topology with all-shared L2 and L3 caches and 27.9% over a topology with per core private L2 cache and shared L3 cache. In addition, we also compared MorphCache to partitioning a single shared cache at each level using promotion/insertion pseudo-partitioning (PIPP) [28] and managing per-core private cache at each level using dynamic spill receive caches (DSR) [18]. We found that MorphCache improves average throughput by 6.6% over PIPP and by 5.7% over DSR when applied to both L2 and L3 caches.

Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy

“…Cache reconfiguration (cache tuning) has been extensively studied, because of the high energy consumption of caches [9], [10], [11], [12], [13], [14]. Dynamic hardware-based methods need to 1) monitor the application to predict the future, and 2) find the best cache configuration effectively.…”

“…Automatic cache hierarchy reconfiguration in hardware has been explored extensively [9], [10], [11], [12], [13], [14]. A survey by Zang and Gordon-Ross [15] summarizes the literature on cache adaptation.…”

Bandwidth-aware reconfigurable cache design with hybrid memory technologies

“…Reconfigurable cache A number of proposals have been made for reconfigurable cache designs targeted at performance optimization [12], [13]. In Ranganathan et al's study, cache memory resources are dynamically divided into multiple partitions used for different processor activities, e.g., instruction reuse [12].…”

“…In Ranganathan et al's study, cache memory resources are dynamically divided into multiple partitions used for different processor activities, e.g., instruction reuse [12]. A recent work proposed to adapt the cache hierarchy topologies to workload cache access behaviors at run-time [13]. Both studies explore the performance benefits by minimizing memory access latency, and do not consider memory bandwidth requirement.…”

Impact of Partitioning Cache Schemes on the Cache Hierarchy of SMT Processors

“…Other research (e.g. [13]) have either focused on increasing performance or reducing energy due to the inherent trade-offs between both of them. Typically, an increase in performance will correspond to an increase in energy consumption.…”