MOS Capacitor Deep Trench Isolation for CMOS image sensors

Ahmed, Nayera; Roy, F.; Lu, G-N.; Mamdy, Bastien; Carrere, J.-P.; Tournier, Arnaud; Virollet, Nicolas; Perrot, C.; Rivoire, M.; Seignard, A.; Pellissier-Tanon, D.; Leverd, F.; Orlando, B.

doi:10.1109/iedm.2014.7046979

Cited by 24 publications

(13 citation statements)

References 3 publications

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“…Additional new imaging technologies besides backside illumination are applicable to GS pixels. The use of capacitive deep trench isolation [20] to create high-density storage capacitors would permit a substantial reduction in pixel pitch without reducing storage capacitance. Photoconductive film technologies are not ideally-suited to Q-GS pixels due to their inability to have zero-kT C charge transfer, but would instead be well-suited to V-GS pixels.…”

Section: Resultsmentioning

confidence: 99%

A Back-Illuminated Voltage-Domain Global Shutter Pixel With Dual In-Pixel Storage

Stark

Raynor

Lalanne

et al. 2018

IEEE Trans. Electron Devices

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A 3.75µm back-illuminated voltage-domain global shutter pixel is presented. The 10T pixel architecture presented contains two independently operable storage branches and supports dual-capture, HDR and CDS functionality. Electronic shielding of the sample diffusions by the vertical photodiode is utilised to reach native and differential parasitic light sensitivities below-73.5dB and-82.5dB at 940nm respectively. A global shutter HDR image capture mode with minimal motion artefacts is also demonstrated.

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Section: Resultsmentioning

confidence: 99%

A Back-Illuminated Voltage-Domain Global Shutter Pixel With Dual In-Pixel Storage

Stark

Raynor

Lalanne

et al. 2018

IEEE Trans. Electron Devices

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“…V S is pinned when the lateral Si-SiO 2 interface is set in inversion mode via CDTI bias control. Such an operation mode cancels the thermal generation of dark current from this interface [11,13]. The parameters involved in relationship (2b) are the key to pixel operation with optimal performance because of the tradeoff between full depletion voltage, transfer efficiency, and full well.…”

Section: Vertical Pinned Photo Gate (Ppg)mentioning

confidence: 99%

“…This makes the transfer path direct in comparison with the 52 conventional implementation of gradual doping and surface TG. Moreover, the proposed pixel 53 structure takes benefit from capacitive deep trench isolation (CDTI), formerly developed for dark 54 current reduction [11] and more recently for fully depleted memories for global shutter applications 55 [7,12]. Its use as a pixel sidewall allows active lateral surface passivation with surface potential 56 pinning for the PPG.…”

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confidence: 99%

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Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications

Roy

Suler

Dalleau

et al. 2020

Sensors

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Tackling issues of implantation-caused defects and contamination, this paper presents a new complementary metal–oxide–semiconductor (CMOS) image sensor (CIS) pixel design concept based on a native epitaxial layer for photon detection, charge storage, and charge transfer to the sensing node. To prove this concept, a backside illumination (BSI), p-type, 2-µm-pitch pixel was designed. It integrates a vertical pinned photo gate (PPG), a buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide–nitride–oxide (ONO) stack. The designed pixel was fabricated with variations of key parameters for optimization. Testing results showed the following achievements: 13,000 h+ full-well capacity with no lag for charge transfer, 80% quantum efficiency (QE) at 550-nm wavelength, 5 h+/s dark current at 60 °C, 2 h+ temporal noise floor, and 75 dB dynamic range. In comparison with conventional pixel design, the proposed concept could improve CIS performance.

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“…However, the implementation of deep trench isolation suffers from the dark current enhancement due to the increase of the interfacial defects at the trench sidewalls. In prior works, the metal-oxide-semiconductor (MOS) capacitor deep trench isolation including doped polysilicon filled trenches [2] and the metal-insulator-silicon deep trench isolation [3] in the accumulation mode were integrated into CMOS image sensors.…”

Section: Introductionmentioning

confidence: 99%

Analysis of pn Junction Deep Trench Isolation with SU-8/SiO2-Liner Passivation in a Linear Butt-Coupled 3D CMOS Si Photodetector Array

Alirezaei

Vierhaus

Burte

2017

Proceedings of Eurosensors 2017, Paris, France, 3–6 September 2017

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Abstract:The realization of 30 µm-deep trench isolation in a linear array of butt-coupled 3D CMOS silicon photodetectors is investigated by implementing the formation of a shallow n + -p junction and SiO2-liner over the trench sidewalls as well as the SU-8 filling trenches for passivation. The dependency of the dark I-V curve on the trench isolation scheme is analyzed by monitoring the dynamic dark I-V measurements of four samples including the schemes of single-trench isolation with different widths and the scheme of double-trench isolation. The highest and the lowest dark currents are measured in the detectors with the widest single-trench isolation and the double-trench isolation, respectively.

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MOS Capacitor Deep Trench Isolation for CMOS image sensors

Cited by 24 publications

References 3 publications

A Back-Illuminated Voltage-Domain Global Shutter Pixel With Dual In-Pixel Storage

A Back-Illuminated Voltage-Domain Global Shutter Pixel With Dual In-Pixel Storage

Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications

Analysis of pn Junction Deep Trench Isolation with SU-8/SiO2-Liner Passivation in a Linear Butt-Coupled 3D CMOS Si Photodetector Array

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