MOSFET devices with polysilicon on single-layer HfO/sub 2/ high-K dielectrics

Kang, Laegu; Onishi, K.; Jeon, Y.; Lee, Byoung Hun; Kang, Chang Seok; Qi, Wenjie; Nieh, R.; Gopalan, Sundararaman; Choi, Rino; Lee, J.C.

doi:10.1109/iedm.2000.904253

Cited by 70 publications

(54 citation statements)

References 4 publications

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“…HfO 2 films are reported to be more resistant to silicide formation than ZrO 2 [50,51]. Only one study in the literature by TALLAN et al reports weight change data that can be used to interpret the point defect chemistry of HfO 2 [43].…”

Section: B) High-k Oxygen Deficiencymentioning

confidence: 99%

Thermodynamic considerations in the stability of binary oxides for alternative gate dielectrics in complementary metal–oxide–semiconductors

Stemmer¹

2004

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

111

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A number of binary oxides have been predicted to be thermodynamically stable in contact with Si and are candidates to replace SiO 2 in CMOS. However, reactions leading to the formation of interfacial silicide, silicate or SiO 2 layers have been reported when these oxides are exposed to high temperatures during device processing. Different pathways have been proposed in the literature to explain these reactions. In this paper, a thermodynamic analysis of the proposed reactions is performed. The analysis includes gaseous species, because typical gate dielectrics are ultra-thin layers and diffusivities for species from the surrounding atmosphere, such as oxygen, may be high. Furthermore, nonstoichiometry of the high-k oxide, as may be resulting from nonequilibrium deposition processes or reducing atmospheres during processing is also considered. Studies are proposed to distinguish between possible reaction mechanisms. Finally guidelines for stable interfaces are presented.3

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Section: B) High-k Oxygen Deficiencymentioning

confidence: 99%

Thermodynamic considerations in the stability of binary oxides for alternative gate dielectrics in complementary metal–oxide–semiconductors

Stemmer¹

2004

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

111

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“…The static dielectric constant of monoclinic HfO 2 ranges from 17 [1,2] to 22 [16]. Throughout this chapter, 'dielectric constant' means relative permittivity k. The absolute permittivity e is the vacuum permittivity e 0 multiplied by this number.…”

Section: Dielectric Constant and Microscopic Polarizationmentioning

confidence: 99%

“…In LSI processes, HfO 2 is deposited either by physical vapor deposition (PVD) such as sputtering [2], chemical vapor deposition (CVD) [1], oxidation of Hf metals [10], or by atomic layer deposition (ALD) [11][12][13][14]. In many cases, HfO 2 forms monoclinic phase just after the deposition process.…”

Section: Dielectric Constant and Microscopic Polarizationmentioning

confidence: 99%

Hafnium-Based Gate Dielectric Materials

Nishiyama

2013

High Permittivity Gate Dielectric Materials

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In this chapter, we focus on hafnium-based gate dielectrics. HfO 2 is regarded as the most promising material for the high-k gate dielectrics owing to its large dielectric constant and large band-gap energy. In the first part of this chapter, these characteristics are addressed in a comparison with SiO 2 and other high-k materials. Thermal stability is a major issue for the application of high-k materials to MOSFETs in LSIs. Although HfO 2 satisfies this requirement, severer process conditions may cause problems even with this material. Suppression of these issues is also addressed in the second part of this chapter. In order to enhance the characteristics of HfO 2 , transformation of the monoclinic phase to the tetragonal and the cubic phases with larger dielectric constant has been pursued recently. We mention the issue in the last part of this chapter. Introductory Remarks and Brief Outline of the ChapterSince the proposal of the materials in the early 2000s [1-3], hafnium-based gate dielectrics have been regarded as the most promising materials for the application to large scale integrations (LSIs). In 2007, Intel announced the start of manufacturing of 45 nm-node LSIs with high-k/metal gate stack, with the remark that the world's first high-k material in commercial production was hafnium-based [4].There are several characteristics that the high-k materials should meet for the application to metal oxide semiconductor field effect transistors (MOSFETs) in LSIs. First, we clarify the properties so that readers can understand their A. Nishiyama

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“…There is a concern that the mobility of the channel carriers may be degraded by interactions with these soft phonons. [8][9][10][11][12][13][14][15][16][17][18] These metal oxides have reasonably high dielectric constants and band gaps (see Figure 3). Both ZrO 2 and HfO 2 devices have demonstrated a many orders of magnitude reduction in gate leakage with an EOT around 1.0 nm and well-behaved t r a n s i s t o r s .…”

Section: Oxygen Diffusion Through the Grain Boundary Of Metal Oxidementioning

confidence: 99%

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

Tseng¹

2010

Solid State Circuits Technologies

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Introduction Motivation for implementing high dielectric constant gate dielectric for advanced CMOS scalingSemiconductor devices need to have good performance, with a low cost and low power dissipation. For decades, research and development of semiconductor processing technology and device integration have focused on enhancing performance and reducing costs using SiO 2 as the gate dielectric and doped polysilicon as the gate electrode. The most effective way to enhance performance and reduce costs is to scale the device gate length and gate oxide. Scaling the gate length results in fabricating more devices per wafer (i.e., increase the device density) and thus reduce the cost per chip, while scaling the gate oxide enhances the drive current and reduces the short channel effects due to gate length scaling. However, as the gate oxide becomes thinner, the power to operate transistors increases because of greater gate oxide leakage current. To resolve this high gate oxide leakage problem, the mechanism of the carriers tunneling through the gate dielectric must be better understood. In an ideal metal-insulator-semiconductor (MIS) device, the current conduction in the insulator should be zero. In a real MIS device, however, current can flow through the insulating film by various conduction mechanisms. The two primary conduction mechanisms for electron tunneling through high quality gate dielectric are discussed below. Direct tunnelingIn a metal-insulator-semiconductor (MIS) stack, when the oxide voltage (V ox ) is smaller than the metal-insulator barrier height, the electron tunnels directly from the metal electrode into other semiconductor electrode through the insulator. This is known as the direct tunneling process. The equation for direct tunneling current density (current normalized by device area) is proportional to

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MOSFET devices with polysilicon on single-layer HfO/sub 2/ high-K dielectrics

Cited by 70 publications

References 4 publications

Thermodynamic considerations in the stability of binary oxides for alternative gate dielectrics in complementary metal–oxide–semiconductors

Thermodynamic considerations in the stability of binary oxides for alternative gate dielectrics in complementary metal–oxide–semiconductors

Hafnium-Based Gate Dielectric Materials

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

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