Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV

Abstract

This work presents the design, the validation and the prototyping of a motion compensation architecture for a H.264/AVC video decoder. The designed architecture supports the main profile level 4.0 and it targets high resolution applications, like HDTV. This design considers the sample processing of the motion compensation block, which includes quarter-pel interpolation, weighted prediction, average to bi-predictive processing and clipping. The architecture processes luma and chroma samples in parallel, with independent luma and chroma datapaths. The design uses a single interpolator to process bi-predictive macroblocks. The design was synthesized to FPGA and standard cell technologies. The synthesis results had indicated that this architecture reaches 100 MHz in both technologies, allowing real time to decode HDTV videos with 1920x1080 pixels. The prototype was targeted to a Xilinx Virtex-II PRO FPGA.

Motion Compensation Hardware Accelerator Architecture for H.264/AVC

“…This filter was designed using the 1-D separability property of 2-D FIR filters. Other MC filter implementations presented in the literature [6,7,8] use a combination of different vertical and horizontal FIR filters serially and target an ASIC implementation. In the architecture of this work, the 2-D interpolation is done by only four FIR filters used for vertical and horizontal filtering.…”