Multi-bit Sigma-Delta TDC Architecture with Improved Linearity

Uemori, Satoshi; Ishii, Masamichi; Kobayashi, Haruo; Hirabayashi, Daiki; Arakawa, Yuta; Doi, Yuta; Kobayashi, Osamu; Matsuura, Tatsuji; Niitsu, Kiichi; Yano, Yuji; Gake, Tatsuhiro; Yamaguchi, Takahiro; Takai, Nobukazu

doi:10.1007/s10836-013-5408-6

Cited by 15 publications

(8 citation statements)

References 6 publications

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“…The application to ADC, sensor interface (for such as capacitor, temperature), all digital PLL, and phase noise/jitter measurement are reported. Varieties of TDC architectures are proposed including flash, Vernier type, and delta-sigma TDCs [2,3]. Many of them can be implemented only with digital circuits.…”

Section: Circuit In Domain 3 (Time-domain Analog Circuit)mentioning

confidence: 99%

“…Circuit nonidealities are measured and they are compensated by digital calculation [2]. This calibration is performed by the circuit itself without the user's recognition.…”

Section: Circuit In Domain 4 (Digital Compensation)mentioning

confidence: 99%

“…(3) Dynamic matching also utilizes redundancy [2,7]. It spreads out the non-idealities of circuit components in frequency domain without measuring them and their spectrum is shaped by their selection method.…”

Section: Circuit In Domain 4 (Digital Compensation)mentioning

confidence: 99%

“…The architecture of TDC is classified as flash TDC and delta-sigma TDC [2]. Flash TDC has two inputs for positive transitions.…”

Section: Tdc Architecturesmentioning

confidence: 99%

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Analog/mixed-signal circuit design in nano CMOS era

Kobayashi

Aoki

Katoh

et al. 2014

IEICE Electron. Express

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This paper describes analog/mixed-signal circuit design in the nano CMOS era. Digitally-assisted analog technology is becoming more important, and as an example, our fully digital FPGA implementation of a TDC with self-calibration is shown. Since pure analog circuits are still present and "good" device modeling is required for their designs, device modeling technology for nano CMOS with complicated behavior is also reviewed.

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Section: Circuit In Domain 3 (Time-domain Analog Circuit)mentioning

confidence: 99%

“…Circuit nonidealities are measured and they are compensated by digital calculation [2]. This calibration is performed by the circuit itself without the user's recognition.…”

Section: Circuit In Domain 4 (Digital Compensation)mentioning

confidence: 99%

Section: Circuit In Domain 4 (Digital Compensation)mentioning

confidence: 99%

“…The architecture of TDC is classified as flash TDC and delta-sigma TDC [2]. Flash TDC has two inputs for positive transitions.…”

Section: Tdc Architecturesmentioning

confidence: 99%

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Analog/mixed-signal circuit design in nano CMOS era

Kobayashi

Aoki

Katoh

et al. 2014

IEICE Electron. Express

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“…TDC applications include phase comparators of all-digital PLLs, sensor interface circuits, modulation circuits, demodulation circuits, as well as TDCbased ADCs [1][2][3]. The TDC will play an increasingly important role in the nano-CMOS era, because it is well suited to implementation with fine digital CMOS processes; a TDC consists mostly of digital circuitry, and resolution improves as switching speed increases.…”

Section: Introductionmentioning

confidence: 99%

Experimental verification of timing measurement circuit with self-calibration

Chujo

Hirabayashi

et al. 2014

19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings

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This paper describes the architecture, implementation and measurement results for a Time-to-Digital Converter (TDC), with histogram-method self-calibration, for high-speed I/O interface circuit test applications. We have implemented the proposed TDC using a Programmable Systemon-Chip (PSoC), and measurement results show that TDC linearity is improved by the self-calibration. All TDC circuits, as well as the self-calibration circuits can be implemented as digital circuits, even by using FPGA instead of full custom ICs, so this is ideal for fine CMOS implementation with short design time.

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