Multi-Drive Stacked-FET Power Amplifiers at 90 GHz in 45 nm SOI CMOS

Agah, Amir; Jayamon, Jefy A.; Asbeck, P.M.; Larson, L.E.; Buckwalter, James F.

doi:10.1109/jssc.2014.2308292

Cited by 70 publications

(8 citation statements)

References 16 publications

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“…This design achieves a 17.6-dBm saturated output power ( ) Psat and 34.6% peak PAE at 45 GHz. A three-stacked class-A PA operating at 90 GHz has also been implemented in a standard 45-nm CMOS SOI technology [19]. In this design, a multidrive technology is proposed to improve the PA's performance.…”

Section: Stacked-transistor Topologymentioning

confidence: 99%

Stacking the Deck for Efficiency: RF- to Millimeter-Wave Stacked CMOS SOI Power Amplifiers

et al. 2016

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T he emerging demand for high-capacity wireless mobile communication and the advent of the Internet of Things and fifthgeneration communication standards have motivated the development of high-performance transceivers. The power amplifier (PA) is the most critical part in the transmit path and dominates the transceiver's performance, including coverage range, data rate, spectrum compliance, and dc power dissipation. Integration capability and the relatively low cost of complementary-metal-oxide-semiconductor (CMOS) technology, on the other hand, have propelled it into the wireless market. CMOS technology enables complete system-on-chip solutions, resulting in ), Yingheng Tang (tang96@purdue.edu), and Saeed Mohammadi (saeedm@purdue.edu) are with the Birck Nanotechnology Center, Purdue University West Lafayette, Indiana, United States.im ag e lic en se d by in gr am pu bl is hi ng

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Section: Stacked-transistor Topologymentioning

confidence: 99%

Stacking the Deck for Efficiency: RF- to Millimeter-Wave Stacked CMOS SOI Power Amplifiers

et al. 2016

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“…To address the tuning range and power efficiency requirements at the same time, a dual-mode, two-stage pre-driving and driving amplifiers will be designed to provide high gain and wide bandwidth. A modified cascode structure in the first stage [13] will save the powerhungry buffer between PA and mixer and offers better isolation between the following stage and the mixer. The unit cell of the PA at the last stage is shown in Fig.…”

Section: B 10-gb/s Bof Soc With Integrated Dual-mode Pamentioning

confidence: 99%

Recent developments in transceiver SoC design for next generation optical networks

Yue

Luo

Zhu

et al. 2015

2015 Asia-Pacific Microwave Conference (APMC)

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This paper presents the ongoing research efforts in optical communication transceiver SoC design for emerging fiberwireless mobile networks and next generation 200/400GbE optical networks using advanced CMOS technologies. First, a 4-Gb/s fiber-to-mm-wave baseband-over-fiber (BoF) modulator SoC using 65-nm CMOS with a fully integrated 850-nm wavelength optical receiver front-end for short-range wireless backhaul connectivity is reviewed. Next, design considerations for an improved 10-Gb/s BoF I/Q modulator SoC with integrated 60-GHz power amplifier is described. Lastly, a novel PAM4/NRZ transceiver architecture featuring BER built-in-self-test is discussed.

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“…When stacked devices are used, the output power is multiple times higher in the condition of an unchanged output current swing. There are quite a few researches about increasing output power of the stacked structure, especially in high frequency . Because devices inherently have a low gain in high frequency, it is hard to output high power.…”

Section: Introductionmentioning

confidence: 99%

“…There are quite a few researches about increasing output power of the stacked structure, especially in high frequency. [7][8][9][10] Because devices inherently have a low gain in high frequency, it is hard to output high power. Another important advantage of the stack structure is widening the amplifier bandwidth.…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of a stacked power amplifier with 196% fractional bandwidth using equivalent circuit model

Wang

et al. 2020

Int J RF Microw Comput Aided Eng

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Stacked structure is a good solution to overcome the low output voltage swing provided by a single device. When several devices are stacked, the bandwidth and output power are multiple times higher. This article analyzes the small‐signal voltage gain of the stacked structure, deriving the gain expression of the high‐frequency model and simplified model. Based on the specific device parameter, the different small‐signal voltage gains between the two models are compared and the designed stacked structure is proved to obtain a flat gain at low frequencies below about 3 GHz. To our best knowledge, this is the first article to analyze the gain flatness of stacked structure with two equivalent circuit models. To verify the stacked theory, a pseudomorphic high‐electron‐mobility transistor（PHEMT） power amplifier (PA) is implemented using 0.25 μm Gallium arsenide (GaAs) technology. The PA achieves an ultra‐high bandwidth of 30 MHz to 3 GHz and a linear gain of 21 dB ± 1.5 dB. At a 16‐V drain bias voltage, a saturated output power of higher than 2 W and a peak power‐added efficiency (PAE) of 44.1% are attained.

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Multi-Drive Stacked-FET Power Amplifiers at 90 GHz in 45 nm SOI CMOS

Cited by 70 publications

References 16 publications

Stacking the Deck for Efficiency: RF- to Millimeter-Wave Stacked CMOS SOI Power Amplifiers

Stacking the Deck for Efficiency: RF- to Millimeter-Wave Stacked CMOS SOI Power Amplifiers

Recent developments in transceiver SoC design for next generation optical networks

Analysis and design of a stacked power amplifier with 196% fractional bandwidth using equivalent circuit model

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