Multi-Layer Model for Stressor Film Deposition

Loiko, K.; Adams, V.; Tekleab, D.; Winstead, B.; Bo, Xiang-Zheng; Grudowski, P. A.; Goktepeli, S.; Filipiak, S.; Goolsby, Brian; Kolagunta, V.; Foisy, M.

doi:10.1109/sispad.2006.282853

Cited by 12 publications

(6 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The intrinsic stress of the passivation layer (σ SiN ) is varied from −2 GPa compressive to +2 GPa tensile to reflect achievable experimental range [5]. A multi-layer deposition scheme consisting in 20 deposition steps is employed for accurate modeling of the mechanical impact of SiN film in the gate region [12].…”

Section: B Simulation Methodologymentioning

confidence: 99%

Local stress engineering for the optimization of p-GaN gate HEMTs power devices

Cosnier

Lucci

Torres

et al. 2017

2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

View full text Add to dashboard Cite

The impact of the built-in stress of the SiN passivation layer on p-GaN gate High Electron Mobility transistors (HEMTs) is investigated through TCAD simulations. Local modifications of electron confinement in the channel area due to stressor deposition can be exploited to increase the threshold voltage independently of the ON-state resistance (up to +1.5 V for tSiN = 200 nm, σSiN = −2 GPa and LG = 0.2 µm). This technique can also be easily combined with an AlGaN backbarrier structure to increase the design margin of p-GaN gate normally-OFF HEMTs.

show abstract

Section: B Simulation Methodologymentioning

confidence: 99%

Local stress engineering for the optimization of p-GaN gate HEMTs power devices

Cosnier

Lucci

Torres

et al. 2017

2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

View full text Add to dashboard Cite

show abstract

“…First we investigate simulated deposition of an intrinsically stressed etch stop liner (ESL) by mono-and multilayer deposition: The latter method is known to produce larger stresses [1][2]. The layout dependence of channel stress is investigated by 3D simulations.…”

Section: Stress Simulationmentioning

confidence: 99%

Nonlinear Piezoresistance Effect in Devices with Stressed Etch Stop Liner

Bach

Liebmann

Nawaz

et al.

Simulation of Semiconductor Processes and Devices 2007

View full text Add to dashboard Cite

Stressed etch stop liners (ESL) are a common way to increase device performance. Here we investigate the layout dependent channel stress for mono-and multi-layer deposition. By means of empirical pseudopotential method full band structures are calculated and based on full band Boltzmann equation mobilities are extracted. We present for the first time nonlinear mobility enhancement maps for two strain components, in channel and out-of-plane direction, showing that for typical ESL conditions both strain components are important for NFET and PFET.

show abstract

“…No stress relaxation processes are taken into account for DSL stress modeling except for the stress relaxation due to free surfaces that are generated in the structure during etching step and other structure formation. 30-multilayer tensile liner deposition technique [8] is employed in DSL process simulation for more accurate pitch dependence modeling. An MC-based model for stress-induced effective electron mobility enhancement is used similar to the model for holes [9].…”

Section: Stress-induced Channel Mobilitymentioning

confidence: 99%

Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs

Kim

Jain

Rhee

et al. 2010

2010 International Conference on Simulation of Semiconductor Processes and Devices

View full text Add to dashboard Cite

The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stressdependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM). The calibration method for the stress-induced channel mobility and the external resistance is proposed using R on -L gate measurements of 32nm-node devices with different gatepitches. The significant performance degradation due to simple gate-pitch scaling is predicted for 20nm-node technology with sub-100nm gate-pitch. I. INTRDUCTIONStress engineering using etch stop liner (ESL) or dual stress liner (DSL) has become one of the main performance element to enhance channel mobility in recent nano-meter scale CMOS technologies [1]. However, as the gate pitch aggressively scales down into sub-100nm regime with continuous technology scaling beyond 32nm-node [2], the two primary concerns and critical challenges for the device performance are being addressed as illustrated in Fig. 1: First, the stress effect associated with liner can be weakened by the narrower distance between neighboring gates which can be the effective space for transferring liner stress into channel. Second, this narrowed gate-space would lead to significant increase in the external resistance, R ext , since the silicide contact length, L con becomes shorter than the contact transfer length and hence will directly increase the contact resistance, R co [3].In this paper, the impact of gate-pitch scaling on device performance element is examined by advanced process and device modeling including the distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The gate length dependence and the pitch dependence and tensile liner stress effect on the internal and external resistances are correlated to measured R on -L gate response of 32nm-node NFETs and applied for 20nm-node technology performance prediction. Effective Space for Contact Resistance and Liner StressL con L gate Gate Pitch Simulation Structure Stress Liner Gate Silicide Figure 1. Schematic illustration of device structure with gate pitch. The effective space transferring liner stress into channel and the silicide contact resistance are scaled with the aggressive shrink of gate-pitch. II. TCAD MODELING AND ANALYSISTCAD process and device modeling using Sentaurus process and device simulator are developed to reflect IBM 32nm high-k/metal gate bulk CMOS technology. Starting from the advanced calibration models, the basic 1-dimentional (1D) and 2-dimentional (2D) parameters are calibrated using experimental data such as device geometries, doping profiles and long and short channel electrical data. A. Impact on Contact ResistanceIn order to understand the gate-pitch dependence on contact resistance, the detailed silicide contact parameter study is ...

show abstract

Multi-Layer Model for Stressor Film Deposition

Cited by 12 publications

References 3 publications

Local stress engineering for the optimization of p-GaN gate HEMTs power devices

Local stress engineering for the optimization of p-GaN gate HEMTs power devices

Nonlinear Piezoresistance Effect in Devices with Stressed Etch Stop Liner

Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs

Contact Info

Product

Resources

About