We report a CMOS-compatible embedded siliconcarbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (Csub) epitaxial Si:C and laser spike annealing (LSA) for increased Csub incorporation. 26% channel resistance (Rch) reduction and ll% Idlin-loff enhancement for 0.5% Csub and 60% Rch reduction for 2.2% Csub are demonstrated.

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We report, for the first time, on the 2-D boundary effects in a high performance 65nm SOI technology with dual Etch Stop Layer (dESL) stressors. 1-D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit design are also discussed. It will be shown that PMOS and ring oscillator performance can be significantly enhanced by optimizing the transverse and lateral placement of the dESL boundary.

Multi-layer simulation is proposed for accurate modeling of stressor film deposition. Multi-layer simulation subdivides a single deposition into a series of deposition and relaxation steps to emulate mechanical quasi-equilibrium during the physical deposition process. Only the multi-layer model is able to simultaneously match the experimental data on drive current vs. etch-stop layer stress, poly pitch, source/drain recess, and spacer stress.

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