Single Metal Gate on High-k Gate Stacks for 45nm Low Power CMOS

Taylor, William J.; Capasso, C.; Min, Bigang; Winstead, B.; Verret, E.; Loiko, K.; Gilmer, D. C.; Hegde, Rama I.; Schaeffer, J.; Luckowski, E.; Martínez, Arturo; Raymond, M.; Happ, C.; Triyoso, Dina H.; Kalpat, S.; Haggag, A.; Roan, D.; Nguyen, Johan; La, L.B.; Hebert, L.; Smith, J.; Jovanovic, D.; Burnett, D.; Foisy, M.; Cave, N.; Tobin, P.J.; Samavedam, S.; White, Saxon William; Venkatesan, S.

doi:10.1109/iedm.2006.346861

Cited by 6 publications

(5 citation statements)

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“…In this case, the RM voltage shows a very rapid initial response, with degradation levels significantly larger than that for NBTI alone. The RM change initially closely follows the kinetics of PBTI degradation, as expected, and is relatively insensitive to the rate of PBTI V t drift in the range that has been measured experimentally 3,4,13,14 . Overall, the V ccmin drift shows weaker time dependence than the t 0.16 characteristic of an NBTI mechanism 12 .…”

Section: A) Pbti Lifetime << Nbti Lifetimementioning

confidence: 66%

“…There are encouraging signs that this is possible for high-k gate dielectric stacks. Recently, several reports have indicated that PBTI can be controlled to be lower than NBTI levels with appropriate choice of high-k materials and processing 13,14,15,16,19 . As we see in figure 10, even WM controlled distributions can show a strong sensitivity to PBTI lifetime changes.…”

Section: Discussionmentioning

confidence: 99%

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Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

Lin

Oates

2007

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual

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We present the results of simulations of voltage-induced V ccmin drift of SRAMs fabricated with high-k gate dielectrics. We show that high-k based SRAMs are fundamentally more susceptible to V ccmin stability problems because PMOS NBTI and NMOS PBTI lead to an additive degradation in the bit-cell read voltage. Given the differing time dependences of the NBTI and PBTI phenomena, the drift of V ccmin is enhanced at much earlier times compared to SRAMs that have SiO 2 gate dielectric only devices. Maintaining V ccmin stability presents a significantly greater challenge for high-k gate dielectrics compared to SiO 2 .

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Section: A) Pbti Lifetime << Nbti Lifetimementioning

confidence: 66%

Section: Discussionmentioning

confidence: 99%

Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

Lin

Oates

2007

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual

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“…We have recently reported that Zr addition into HfO 2 leads to improved HfO 2 reliability, mobility, and scalability. [1][2][3][4] Hf x Zr 1−x O 2 transistors with excellent electrical characteristics have recently been fabricated. [1][2][3][4] Among the various methods available to deposit thin high-k films, atomic layer deposition ͑ALD͒ is considered the most promising due to its precise thickness control, easy composition control, excellent conformality, and low deposition temperature.…”

mentioning

confidence: 99%

“…[1][2][3][4] Hf x Zr 1−x O 2 transistors with excellent electrical characteristics have recently been fabricated. [1][2][3][4] Among the various methods available to deposit thin high-k films, atomic layer deposition ͑ALD͒ is considered the most promising due to its precise thickness control, easy composition control, excellent conformality, and low deposition temperature. ALD is a chemical gas-phase self-limiting deposition based on alternative saturative surface reactions.…”

mentioning

confidence: 99%

Physical and Electrical Properties of Atomic-Layer-Deposited Hf[sub x]Zr[sub 1−x]O[sub 2] with TEMAHf, TEMAZr, and Ozone

Triyoso¹,

Gregory²,

Park

et al. 2008

J. Electrochem. Soc.

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In this work, physical and electrical characteristics of atomic-layer-deposited HfxZr1−xnormalO2 formed using tetrakis-ethyl methylaminohafnium (TEMAHf), tetrakis-ethylmethylaminozirconium (TEMAZr), and ozone are reported. Confirming Zr addition, film densities decrease with increasing Zr content. A slight increase in interfacial layer thickness is observed for ZrO2 after high-temperature annealing. All films remain smooth and void-free after high-temperature annealing. Tetragonal phase stabilization is observed with increasing Zr content. Carbon impurities are low and independent of Zr content. HfxZr1−xnormalO2 transistors and capacitors are fabricated for electrical characterization. Well-behaved capacitance–voltage characteristics are observed for all devices. Only a slight increase in gate leakage current is observed as Zr content is increased from <2% (HfO2) to ∼50% (Hf0.5Zr0.5normalO2) . HfxZr1−xnormalO2 devices have ∼50mV lower threshold voltage than HfO2 devices. High field mobilities of HfxZr1−xnormalO2 devices with 50 and 60% Zr content are higher than HfO2 or ZrO2 . All these results indicate HfxZr1−xnormalO2 is a promising dielectric for SiO2 replacement.

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“…A poly-Si/TaC single-metal gate, 40 nm in length, has been achieved. 1) The profile control of poly-Si/TiN gate and TiN/TaSiN full-metal gate has been reported. 2,3) However, their gate length was about 100 nm.…”

Section: Introductionmentioning

confidence: 99%

Etch Profile Control of W/TiN/HfSiON and W/TaSiN/HfSiON Full-Metal Gates

Ono¹,

Aoyama²,

Nara³

2009

Jpn. J. Appl. Phys.

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W/TiN/HfSiON and W/TaSiN/HfSiON, equivalent oxide thickness (EOT) 1 nm, full-metal gate stacks were etched using CF 4 and SF 6 based gas chemistries. Vertical profiles were achieved for both TiN and TaSiN metal gates with gate lengths of 20 nm by controlling gas chemistry and pressure. The etch condition was changed from the high-pressure region to the low-pressure region immediately before the appearance of the underlying TaSiN surface by monitoring the thickness of the W layer to take advantage of both high-and low-pressure plasma characteristics.

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Single Metal Gate on High-k Gate Stacks for 45nm Low Power CMOS

Cited by 6 publications

References 0 publications

Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

Physical and Electrical Properties of Atomic-Layer-Deposited Hf[sub x]Zr[sub 1−x]O[sub 2] with TEMAHf, TEMAZr, and Ozone

Etch Profile Control of W/TiN/HfSiON and W/TaSiN/HfSiON Full-Metal Gates

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