We present the results of simulations of voltage-induced V ccmin drift of SRAMs fabricated with high-k gate dielectrics. We show that high-k based SRAMs are fundamentally more susceptible to V ccmin stability problems because PMOS NBTI and NMOS PBTI lead to an additive degradation in the bit-cell read voltage. Given the differing time dependences of the NBTI and PBTI phenomena, the drift of V ccmin is enhanced at much earlier times compared to SRAMs that have SiO 2 gate dielectric only devices. Maintaining V ccmin stability presents a significantly greater challenge for high-k gate dielectrics compared to SiO 2 .

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