Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

Abstract

We present the results of simulations of voltage-induced V ccmin drift of SRAMs fabricated with high-k gate dielectrics. We show that high-k based SRAMs are fundamentally more susceptible to V ccmin stability problems because PMOS NBTI and NMOS PBTI lead to an additive degradation in the bit-cell read voltage. Given the differing time dependences of the NBTI and PBTI phenomena, the drift of V ccmin is enhanced at much earlier times compared to SRAMs that have SiO 2 gate dielectric only devices. Maintaining V ccmin stability presents a significantly greater challenge for high-k gate dielectrics compared to SiO 2 .

Reliability of silicon integrated circuits

“…SRAM circuits are particularly vulnerable to BTI effects, since differing amounts of V th drift in the PMOS pull-down (NBTI) and NMOS pull-up transistors (PBTI) of the bit cell lead to a reduction of the static noise margin of the SRAM cell [48,49]. As Figure 7.8 shows, the minimum voltage required to read the memory (V min ) increases, while that to write the memory decreases.…”

Technology variability from a design perspective

“…Negative BTI (NBTI) is caused by trapping of the carriers in the PMOS gate interfaces under high biases, which causes threshold increase and degraded current. BTI, which only affected PMOS transistors in Si-O 2 gate stacks, now affects both NMOS and PMOS transistors in high-K metal gate devices [12].…”

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

“…Because SRAM stability is extremely sensitive to transistor mismatches, BTI and HCI pose a significant problem to SRAM reliability [4][5][6]. In [7][8][9], the authors analyzed SRAM stability by assuming two ideal stress conditions, that is, static stress (0% or 100% duty cycle) and alternating stress (50% duty cycle). However, the realistic stress conditions of the SRAM cells really depend on customer usages (workload).…”