Multi-Level NAND Flash Memory with 63 nm-Node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure

Abstract

For the first time, multi-level NAND flash memories with a 63 nm design rule are developed successfully using charge trapping memory cells of Si/SiO 2 /SiN/Al 2 O 3 /TaN (TANOS). We successfully integrated TANOS cells into multi-gigabit multi-level NAND flash memory without changing the memory window and circuit design of the conventional floating-gate type NAND flash memories by improving erase speed. The evolved TANOS cells show fourlevel cell distribution which is free from program disturbance and a charge loss of less than 0.4 V at high temperature bake test.

SONOS-Type Flash Memory Cell With Metal$/\hbox{Al}_{2}\hbox{O}_{3}/ \hbox{SiN}/\hbox{Si}_{3}\hbox{N}_{4}/\hbox{Si}$ Structure for Low-Voltage High-Speed Program/Erase Operation

“…We achieved the programmed V TH of +2.8 V with +15 V for 100 µs, and erased V TH of −1 V (a total V TH shift of 3.8 V) with −10 V for 10 ms. This erase voltage is much lower than that of the conventional floating-gate and TANOS devices and even lower than that of the device that has thinner tunneling oxide, which require higher than −14 and −17 V for 10 ms to acquire the memory window of 4 V [1], [2]. This low erase voltage arises from the low barrier height of Si 3 N 4 as tunnel dielectric, which is consistent with the simulation results shown in Fig.…”

Reliability of 3D NAND Flash Memories

“…In NAND flash cells, program and erase operations rely on charge transport through thin oxides; this is accomplished via Fowler-Nordheim (FN) tunneling into/from a storage layer, which can be either a polysilicon FG [1] or an interfacial trapping layer in CT technology [2,3]. Electron tunneling is responsible for a slow, but continuous, oxide wear out because of traps creation and interfacial damages; as a result, there might be charge trapping/detrapping into the tunneling oxide or undesired charge flowing into/from the storage layer.…”

Characterization of cell to cell interference in TANOS NAND flash memory

“…Since the storage layer is thin nitride (an insulator) layer, the cell to cell interference is negligible compared with that of conventional FG NAND. In TANOS NAND technologies which have a minimum feature size of more than 60 nm, the cell to cell interference was negligible as aggressor cells are programmed [5]. However, the cell to cell interference was appreciable in 40 nm TANOS NAND flash memory.…”

“…So, it is considered as the most promising devices to replace FG NAND flash memory. In 60 nm TANOS NAND flash memory, the cell V th distribution in the inhibit strings was not influenced during the programming of adjacent string [5]. It is expected that the interference becomes appreciable with scaling-down.…”