For the first time, multi-level NAND flash memories with a 63 nm design rule are developed successfully using charge trapping memory cells of Si/SiO 2 /SiN/Al 2 O 3 /TaN (TANOS). We successfully integrated TANOS cells into multi-gigabit multi-level NAND flash memory without changing the memory window and circuit design of the conventional floating-gate type NAND flash memories by improving erase speed. The evolved TANOS cells show fourlevel cell distribution which is free from program disturbance and a charge loss of less than 0.4 V at high temperature bake test.

The data retention characteristics of nitride-based charge trap memories using metal-oxide-nitride-oxide-silicon (MONOS) structures employing high-k dielectrics and high-work-function metal gates have been investigated. The fabricated MONOS devices with structures of TaN/Al 2 O 3 /Si 3 N 4 /SiO 2 /p-Si show fast program/erase characteristics with a large memory window of greater than 6 V at program and erase voltages of AE18 V. From a bake retention test at high temperatures (200, 225, 250, and 275 C), it is expected to take more than 40 years to lose less than 0.5 V charge loss at 85 C. In this paper, we present an optimized cell structure for both improved data retention and erase speed, as well as a systematic study on the charge decay process in MONOS-type flash memory for high-density device applications.

A new bias pulse method was proposed to suppress read disturbance in unselected strings of 3-D stack NAND flash memories. Using the proposed read method, we could suppress effectively a large cell V th shift generated by boosting hot carrier injection. As a result, the cell V th shift in unselected string is quite similar to normal read disturbance in select string. The proposed read method was verified by both measurement and simulation.Index Terms-NAND flash, read disturb, 3-D stack NAND flash, hot carrier injection.

We present the TANOS (Si-Oxide-SiN-Al 2 O 3 -TaN) cell with 40 Å-thick tunnel oxide erased by Fowler-Nordheim (FN) tunneling of hole. Thanks to introducing high-k dielectrics, alumina (Al 2 O 3 ) as a blocking oxide, the erase threshold voltage can be maintained to less than -3.0 V, meaning hole-trapping in SiN. We extracted the nitride trap densities of electron and hole for the TANOS cell. It is demonstrated that the TANOS structure is very available to investigate the trap density with shallower energy. The energy level of hole trap (1.28 eV) is found to be deeper than that of electron (0.8 eV). As the cycling stress is performed, persistent hole-trapping is observed unlike endurance characteristics of conventional floating-gate cell. The hole trapping during the cycling stress can be attributed to two possibilities. The injected holes are trapped in neutral trap of tunnel oxide and residue of holes which is not somewhat compensated by injected electrons may be accumulated in SiN. It is demonstrated the erase operation of the TANOS cell is governed by Fowler-Nordheim tunneling of hole due to the field concentration across the tunnel oxide.

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