Suppression of Read Disturb Fail Caused by Boosting Hot Carrier Injection Effect for 3-D Stack NAND Flash Memories

Abstract

A new bias pulse method was proposed to suppress read disturbance in unselected strings of 3-D stack NAND flash memories. Using the proposed read method, we could suppress effectively a large cell V th shift generated by boosting hot carrier injection. As a result, the cell V th shift in unselected string is quite similar to normal read disturbance in select string. The proposed read method was verified by both measurement and simulation.Index Terms-NAND flash, read disturb, 3-D stack NAND flash, hot carrier injection.

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…Similar considerations apply to vertical-gate structures, in which channel arrays are horizontally stacked with vertical WLs [361,362]. A study of read disturb in 3D NAND was presented in [363], highlighting an enhanced disturb on unselected cells due to channel boosting. A related effect was discussed in [364], where it is shown that the trailing edge of the WL bias at the end of a read phase can draw the channel potential negative, as it becomes floated when high-V T cells along the string are turned off.…”

Diode-Type NAND Flash Memory Cell String Having Super-Steep Switching Slope Based on Positive Feedback

“…Pass and SL biases for the FET-type string are 6.5 and 2 V, respectively. be performed to reduce the high electric field and the bandto-band generation rate, which can incur unwanted charge trapping into the WL k−1 cell [19]. Fig.…”

“…2, in case V WL6 is smaller than V ON of the WL 6 cell. The channel potentials of WL 5 and WL 6 cells are given by [19], [20] where C dep is the depletion capacitance, C ONO is the capacitance of gate dielectric (oxide/nitride/oxide), and V th_WL5 and V th_WL6 are the threshold voltages of WL 5 and WL 6 cells, depending on the stored charges in the storage layer, respectively. Q is the electron charge, which is supplied to the channel of WL 5 and WL 6 cells during the precharge step.…”

Optimizing read disturb phenomenon with new read scheme by partial-boosting channel in 3-D NAND Flash memories

“…Therefore, structure with the 3-D vertical channel and stacked Word-lines (WLs) was applied to the NAND Flash memory and the number of string/BL is increased [1,2,3,4,5]. This structure caused phenomenon different from soft programming such as hotcarrier injection (HCI) induced read disturb in unselected strings [6,7].…”

“…Some electrons are accelerated in the spacer region and become hot carriers, which makes a large shift of threshold voltage (Vth) in two neighbor WLs [9,10]. Many efforts have been made to solve this HCI-induced read disturb [6,11,12]. For example, drain select line (DSL) and source select line (SSL) are turned on for long time with high voltage to make lower channel potential difference than conventional read operation (see Fig.…”