Multi-level p-channel flash memory

Lin, Frank Ruei-Ling; Wang, Yen-Sen; Hsu, Chih-Wei

doi:10.1109/icsict.1998.785921

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…5. A 3 V shift in 1 s can be achieved with a control gate bias of 8 V. This device possesses multilevel programming capability, with uniform 1.3 V shift in for each 1 V increment in [4]. Thus, two-bit storage per cell is possible for significant improvement in storage density.…”

Section: Resultsmentioning

confidence: 99%

JVD silicon nitride as tunnel dielectric in p-channel flash memory

She

King

et al. 2002

IEEE Electron Device Lett.

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High-quality jet vapor deposition nitride is investigated as a tunnel dielectric for flash memory device application. Compared to control devices with SiO 2 tunnel dielectric, faster programming speed as well as better retention time are achieved with low programming voltage. The p-channel devices can be programmed by hot electrons and erased by hot holes, or vice versa. Multilevel programming capability is shown.

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Section: Resultsmentioning

confidence: 99%

JVD silicon nitride as tunnel dielectric in p-channel flash memory

She

King

et al. 2002

IEEE Electron Device Lett.

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“…On the other hands, recently, in order to achieve high performance and highly reliable embedded Flash memory, lots of interests have been focused on p-channel SONOS memory devices. [13][14][15] Especially, three superior characteristics of p-channel Flash memory (low voltage operation, high speed programming, and low power consumption) have been emphasized. 16,17) In order to achieve hot electron injection in SiN layer, low gate voltage setting is required and makes it possible to attain low voltage operation at the gate.…”

Section: Introductionmentioning

confidence: 99%

Study Trapped Charge Distribution in P-Channel Silicon–Oxide–Nitride–Oxide–Silicon Memory Device Using Dynamic Programming Scheme

Chiu

Lee

et al. 2013

Jpn. J. Appl. Phys.

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In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.

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