In this paper, the process-induced I-V characteristics and reliability degradations for both of nMOSFETs and pMOSFETs on strained Si have been fully characterized. Contrary to nMOSFETs, apparent device reliability degradation of pMOSFETs at high temperature was observed. The degradation mechanism is attributed to SiGe substrate-induced donor-we interface state generation along oxideiSi interface. From manufacturing point of view, it is considered that not only the strained-induced misfit dislocations but also the MOSFETs' reliability degradations should be considered for Si-strained technology with SiGe substrate. [Kejwurds: struined Si, relaxed Silicon-Germanium, misfit dislocation, n-lp-MOSFET, mobility, hot carrier injection and bias temperature stress.]To enhance transistor performance, transistors on strained silicon with relaxed SiGe have been proposed, since SiiSiGe lattice mismatch will induce biaxial tensile strain and then improves the electron and hole mobility [1]-[7]. However, these reports just focused on how to achieve the best performance and reduce the junction leakage due to misfit dislocations between strained Si and relaxed SiGe. To our best knowledge, only one paper discussed the nMOSFET's hot carrier injection (HCI) reliability concems induced by SiGe strained-Si [SI. The authors considered the degradation was due to larger substrate current and very large positive activation energy (Ea) at low drain bias. However, the lifetime will be very worse if we use the extracted Ea value to predict the lifetime at room temperature.In this study, we characterized the I-V characteristics of nipMOSFETs at different temperature. in addition, we also reexamined the hot carrier degradation and evaluated bias temperature instability of nMOSFETs and pMOSFETs, respectively. Contrary to the results in reference [8], our data show nMOSFETs can still have acceptable hot carrier degradation immunity even at high temperature operation. However, pMOSFETs will have severe reliability degradation for both of WCI and negative bias temperature stress (NBTS). Based on the C-V characteristics, we attribute the worse HCI and BTS degradations of pMOSFETs to that mote of the interface states locate along oxidehtrained Si interface after full processing, and most of these interface states belong to donor-type. Finally, we also illustrate that the manufacturing window decided by driving capability, junction leakage and device reliability.
EXPERIMENTALIn this study, transistors were processed with a standard sub-0. I prn technology. The key process parameters included gate oxide thickness 1.7nm and on mask gate length 0.1 lum. To compare the typical device characteristics of transistors fabricated on bulk Si substrate with SiCe strained-Si substrate, large transistors with channel length and width as lOum were used to evaluate the mobility enhancement, saturation current (Idsat) and C-V characteristics. In addition, transistors with minimum channel length 0. I lum were also used for the HCI and BTS evaluation. In addition, dev...
