Multi-rate phase interpolator for high speed serial interfaces

Multi-data rate receiver for high-speed serial interfaces

“…These topologies are known as current mode or analog phase interpolators and they are usually employed in high speed systems which already include current-mode logic circuits to take advantage of all of their benefits. Analog PIs are mainly constructed by cml-type blocks, as shown in Figure 5.4 [157].…”

“…4(b). This, however, highly loads the output node of the interpolator and the preceding stages, due to the large number of required differential pairs and reduces in this way their bandwidth [157]. As a result, this method is not preferred.…”

“…The main advantage of analog PIs is the ability for high frequency operation. In high frequencies, the parasitic capacitances, which are combined with the termination resistors, increase the output slopes which is beneficial for interpolation, as it will be explained later [157]. Their main disadvantages are the difficulty to achieve good phase interpolation linearity over a wide frequency range and the relatively large settling time over reasonable static power consumption which affects the system power efficiency [36], [123], [153], [157].…”

“…The second category includes voltage-mode PIs, based on CMOS logic circuits like inverters or buffers [117], [118], [119], [157]. The employment of CMOS-logic cells simplifies the overall design, but the main concept remains the same.…”

“…More phase steps can only be generated by connecting more blocks in series making a tree structure as illustrated in Figure 5.5(a). However, in tree architectures when more resolution is required the extra PI units significantly increase the integration area and the power consumption [157]. This issue can be solved by using the cascaded topology illustrated in Figure 5.5(b).…”