Multi-standard reconfigurable motion estimation processor for hybrid video codecs

Nunez-Yanez, Jose; Spiteri, Trevor; Vafiadis, George

doi:10.1049/iet-cdt.2009.0070

Cited by 6 publications

(8 citation statements)

References 9 publications

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“…Hence, considering a reconfigurable multiplier having 16-bit input (X) and the 16-bit coefficient (H), the worst case condition will occur for the coefficient of values 16'HFFFF. Shift and add based multiplication operation between the inputs (X) with this coefficient (16'HFFFF) values can be written as (1) [13]: Considering the BCS of 3-bit lengths the partial product generated from each BCS will be as (2) Substituting equation (2) in equation (1) one gets (3)…”

Section: Concepts and Complexity Analyses Of Fixed Bit Bcse (Fbcsmentioning

confidence: 99%

“…Moreover, systems like Software Defined Radio (SDR) [1] and multi-standard video codec [2] need a reconfigurable FIR filter with dynamically programmable filter coefficients, interpolation factors and lengths which may vary according to the specification of different standards in a portable computing platform. Significant applicability of an Manuscript efficient reconfigurable FIR filter motivates the system designer to develop the chip with low cost, power, and area along with the capability to operate at very high speed.…”

Section: Introductionmentioning

confidence: 99%

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An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

Hatai

Chakrabarti

Banerjee

2015

IEEE Trans. Circuits Syst. I

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The Power is the main challenging factor in very large scale integrated circuits. Transpose form fir filters produce better results compared to the direct form FIR filters for reconfigurable applications. In the existing method, the possibility of realization of FIR filter in transpose form configuration Using Common Sub expression Elimination was explored.. This paper explains comparison of two different architectures for low complexity FIR filters namely Constant shift method (CSM), programmable shift methods (PSM) and vertical-horizontal binary common sub-expression elimination (VHBCSE). The FIR filters can efficiently implemented by using constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) instead of common sub-expression elimination (CSE). This technique is capable of reducing the average probability of using the switching activity of the multiplier block adders compared to that of existing algorithm i.e., Binary Common sub-expression elimination (BCSE) algorithm. The filter architecture is capable of operating for word length filter coefficient without any overhead in the hardware circuitry. This VHBCSE produce the better power results. Keywords: Constant shift method (CSM), Programmable shift method (PSM), Vertical-Horizontal Binary Common Sub-expression Elimination (VHBCSE), and Binary common sub-expression elimination (BCSE.) I. INTRODUCTION FINITE-IMPULSE response (FIR) digital filter plays an important role in digital signal processing applications, such as speech processing, loud speaker equalization, echo cancellation, adaptive noise cancellation, and various communication applications, including software-defined radio (SDR) and so on. These applications require FIR filters of large order to meet the frequency specifications. These filters need to support high sampling rate for very high-speed digital communication. The number of multiplications and additions required for each filter output, increases linearly with the filter order. Since there is no redundant computation available in the FIR filter algorithm, real-time implementation of a large order FIR filter in a resource contained environment is daunting and challenging task.

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Section: Concepts and Complexity Analyses Of Fixed Bit Bcse (Fbcsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

Hatai

Chakrabarti

Banerjee

2015

IEEE Trans. Circuits Syst. I

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“…A data cache-based interleaved memory structure is used in [29], which allows parallel access to 16 pixels. LiquidMotion [27], [30] uses 64-bit-wide data buses to access the reference and MB memory, and each execution unit in LiquidMotion has its own copy of the point memory, which is 256 × 16 bits in size and contains the information of the search patterns. These wide data buses and point memories allow parallel operation of each execution unit.…”

Section: Performance Comparisonsmentioning

confidence: 99%

“…As a result, these ME algorithms require fewer cycles compared with those in [28]. Nunez-Yanez et al proposed another SAD instruction [30] that can operate on 16 × 16 and 8 × 8 blocks. In addition, its integer ME (IME) hardware is reconfigurable and thus, the number of SAD units can be changed according to the search points.…”

Section: Introductionmentioning

confidence: 99%

MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor

Kim

Sunwoo

2013

IEEE Trans. Circuits Syst. Video Technol.

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This paper proposes a new motion estimation (ME)-specific instruction-set processor (MESIP) with a novel search scan order with high data reusability, to efficiently implement various advanced ME algorithms. The proposed ME-specific instructions can be selectively used for ME algorithms. The novel data-reusing search scan order, called center biased search scan (CBSS), exploits the symmetry of the search pattern to reduce redundant data loading on MESIP by about 26.9% and 16.1% compared with raster scan and snake scan, respectively. MESIP has been implemented with IBM's 90-nm CMOS technology and has 203K gates excluding memory. Simulation results show that the proposed MESIP can reduce the number of required instructions by up to 18.9% compared with existing ME processors. Moreover, MESIP achieves comparable performance even with ME ASICs and hence may be quite suitable for a low-power and high-performance ME implementation.Index Terms-Application-specific instruction-set processor (ASIP), configurable architecture, low-power design, motion estimation/motion compensation (ME/MC), search scan order.

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“…One of the aims of the proposed SVC scheme was to keep the complexity as low as possible to make the algorithm suitable for hardware implementation, complementing an existing body of work on compression [19,20] and motion estimation [21] in hardware.…”

Section: Introductionmentioning

confidence: 99%

Scalable video coding with multi-layer motion vector palettes

Spiteri¹,

Nunez-Yanez²

2012

IET Image Process.

Self Cite

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Scalable video coding (SVC) allows an encoded bitstream to be brought down in scale or quality without the need for further processing. This study presents a wavelet-based motion-compensated system for SVC. The motion vectors are encoded in a scalable manner that employs a palette of motion vectors split into layers, which gives good scalability and low bit rates. The algorithms were designed to keep the complexity and memory requirements low, making the system suitable for hardware implementation. Experimental results show that the compression performance of the proposed system compares well with the joint scalable video model reference software for scalable video extension to H.264/AVC, while providing a finer and larger range of quality scalability.

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Multi-standard reconfigurable motion estimation processor for hybrid video codecs

Cited by 6 publications

References 9 publications

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor

Scalable video coding with multi-layer motion vector palettes

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