Multi-TAP connection architectures for application specific integrated circuits

Margulis, A.; Akselrod, D.

doi:10.1109/ccece.2008.4564819

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Cited by 2 publications

(3 citation statements)

References 14 publications

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“…This approach has been introduced over a decade ago [5]. Since then, many multi-TAP architecture options have been introduced [2], [6].…”

Section: Dfx Control Architecture Evolutionmentioning

confidence: 99%

Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs

et al. 2013

Self Cite

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“…This approach has been introduced over a decade ago [5]. Since then, many multi-TAP architecture options have been introduced [2], [6].…”

Section: Dfx Control Architecture Evolutionmentioning

confidence: 99%

Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs

et al. 2013

Self Cite

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“…Other than the challenges on testing the interconnect architecture, the ability to test IPs is also critical during platform validation and high volume manufacturing [8], [9]. Several design-fortestability (DFT) techniques have been proposed for NoC testing [10], [11].…”

Section: Introductionmentioning

confidence: 99%

“…Typical cores nowadays have standard built-in TAP to facilitate both on-chip testing and also design-for-debug (DFD) implementation and reuse. This development has triggered advancement of several multi-TAP architectures that makes use of this embedded debug feature in IP to provide debug facility for any number of IPs in a SoC by using the same number of external pins [8]. At the same time, promoting future IPs to be designed with this TAP feature, selecting the correct architecture is considered a key point in reduction of testing and debugging efforts, decreasing test time, as well as allowing effortless architectural reuse across different platforms and designs.…”

Section: Introductionmentioning

confidence: 99%

Multi-TAP architecture for IP core testing and debugging on network-on-chip

Rajagopal

Ooi

Marsono

2011

TENCON 2011 - 2011 IEEE Region 10 Conference

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With the trend to deep-sub-micron (DSM) technology, the ability for post-fabrication testing has become a big concern for system-on-chip (SoC) designers. The testing problem of network-based SoCs is categorized into two major parts, intellectual property (IP) core testing and communication infrastructure testing. This paper presents an IP testing platform using multiple-test-access-port (multi-TAP) for mesh-based networkon-chip (NoC). In our approach, the TAP ports of IPs are connected together in a daisy chain. In addition, IEEE 1149.1 standard (JTAG) is used to connect TAPs of IPs to the external tester. The proposed platform provides comprehensive testing and debugging for each individual IP without incurring dependency to other IPs. The main advantage of the proposed platform is the ability to bypass the IPs which are not involved in the process of testing. Hence, It reduces the required number of clock cycles to send test vectors to the IP/IPs under test.

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Multi-TAP connection architectures for application specific integrated circuits

Cited by 2 publications

References 14 publications

Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs

Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs

Multi-TAP architecture for IP core testing and debugging on network-on-chip

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