Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout

Luk, W.K.; Dean, A.; Mathews, John W.

doi:10.1109/iccad.1989.76998

Cited by 7 publications

(4 citation statements)

References 10 publications

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“…A hierarchical approach to floorplanning has been reported in [17], and research on this class of floorplans has some encouraging results [31] [35][18] [27]. The partitioning based hierarchical floorplanning has been studied in [4][15] [16]. Simulated Annealing is a technique used to solve general optimization problems, floorplanning problems being one of them [32].…”

Section: Introductionmentioning

confidence: 99%

Fast floorplanning for effective prediction and construction

Ranjan¹,

Bazargan²,

Ogrenci³

et al. 2001

IEEE Trans. VLSI Syst.

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Floorplanning is a crucial phase in VLSI Physical Design. The subsequent placement and routing of the cells/modules are coupled very closely with the quality of the floorplan. A widely used technique for floorplanning is Simulated Annealing. It gives very good floorplanning results but has major limitation in terms of running time. For more than tens of modules Simulated Annealing is not practical. Floorplanning forms the core of many synthesis applications. Designers need faster prediction of system metrics to quickly evaluate the effects of design changes. Early prediction of metrics is imperative for estimating timing and routability. In this work we propose a constructive technique for predicting floorplan metrics. We show how to modify the existing top-down partitioning based floorplanning to obtain a fast and accurate floorplan prediction. The prediction gets better as number of modules and flexibility in their shapes increases. We also explore the applicability of traditional Sizing Theorem when combining two modules based on their sizes and interconnecting wirelength. Experimental results show that our prediction algorithm can predict the area/length cost function normally within 5-10% of the results obtained by Simulated Annealing and is, on the average, thousand times faster.

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Section: Introductionmentioning

confidence: 99%

Fast floorplanning for effective prediction and construction

Ranjan¹,

Bazargan²,

Ogrenci³

et al. 2001

IEEE Trans. VLSI Syst.

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“…Furthermore, in this paper we will show that N-way partitioning by recursive application of mincut bi-partitioning yields inferior results compared to our new approach. Partitioning has been used as a tool for floor-planning [2,4,5] and for combined floorplanning and routing [3]. Simulated annealing has been applied to a clustered netlist for standard cell placement in [21] and in a multi-level placement technique [22].…”

Section: Previous Workmentioning

confidence: 99%

A timing driven N-way chip and multi-chip partitioner

Roy

Sechen

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

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With the growing complexity of integrated circuits and the advent of new technologies and new generations of packaging technologies, an essential physical design tool is a flexible physical panitioner. We therefore present a timing driven n-way chip and multi-chip partitioner which we call Tomus. The panitioner enables an automatic layout package to I ) divide and conquer the physical design process of Field Programmable Gate Array (FPGA) circuits or mixed macro/standard cell circuits and 2 ) physically partition a circuit onto n chips for a multichip package. Using a two-phased natural and adaptive clustering method, the annealing-based N-way partitioner executes four to 22 times faster with improved partitioning results. The placement results for industrial FPGAs were improved by 9Wo over the only available industrial placement tool. Our partitioner outpevormed an industrial FPGA partitioner by 95% in MCM partitioning.

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“…Then, we need to solve the problem of chip partition. There are such floorplanning algorithms hy using enumerated method [5,6] and mixed mode method [ 10, 111.…”

Section: B Chip Partitionmentioning

confidence: 99%

Data-path layout design inside SOC

Tong

Hong

Cai

et al.

IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions

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As more data-path stacks are integrated into system-on-a-chip (SOC), data-path is becoming a critical part ofthe whole giga-scale integrated circuits (GSI) design. The traditional layout design methodology can not satisfy the data-path performance requirements because it has no knowledge of the data-path bit-sliced structure and the strict performance (such as timing, coupling, and crosstalk) constraints. In this paper, we address fundamental problems in layout design automation of data-path. We concentrate on the key technologies in data-path layout design. We also discuss the corresponding researches and solutions in this research field.

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Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout

Cited by 7 publications

References 10 publications

Fast floorplanning for effective prediction and construction

Fast floorplanning for effective prediction and construction

A timing driven N-way chip and multi-chip partitioner

Data-path layout design inside SOC

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