Multibit Delta-Sigma Modulator With Two-Step Quantization and Segmented DAC

Cheng, Yongjie; Petrie, C.S.; Nordick, B.; Comer, Douglas E.

doi:10.1109/tcsii.2006.881825

Cited by 26 publications

(14 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A second disadvantage is that it converts the mismatch into noise that also affects the performance of the ADC. Because of these facts, the solutions without DEM, i.e., consuming less power, for example [35][36][37], are gaining more interest. In the "DEM-free" architectures, the digital ∆Σ is used to reduce the resolution of the outermost feedback signal since the non-linearities in the outermost feedback appear at the ADC output with the same transfer function as the input.…”

Section: Motivationmentioning

confidence: 99%

“…The utilization of digital ∆Σ is not limited to digital-to-analog conversion only. It is also used in analog-to-digital conversion [35][36][37][38], in phase-locked loops [39][40][41][42][43][44][45][46][47][48][49], and as a source to generate dithering signals [50][51][52][53][54][55][56], to segment the DAC further [57,58] and in multiple-input, multiple-output transceivers [59], etc. All of the above signal processing blocks are used for narrow-, wideand ultra-wide-band applications like digital audio [60][61][62], handsets [63][64][65], biomedical [66,67], TV [68][69][70], digital radio tuners [71,72] and wireless infrastructures [73][74][75].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

View full text Add to dashboard Cite

Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

show abstract

Section: Motivationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

View full text Add to dashboard Cite

show abstract

“…This additional delay makes it possible to apply DEM to shape the first stage DAC noise digitally. Even though two half-delay integrators are utilized in Fig.2, this modulator has the same form of noise/signal transfer function as a standard second order sigma-delta modulator [4]. Similar to using two-step quantization to reduce the number of comparators in the flash ADC, one can use the segmented DACs to greatly reduce the number of unit elements in the DAC.…”

Section: A Thedelta-sigma Modulator With Two-step Quantizermentioning

confidence: 99%

“…Modulators with two-step quantizers are the other choice for delta sigma ADCs with multi-bit quantizers [3,4]. The main problem of these modulators is implementation of segmented input DAC; the performance of these modulators is limited to the linearity of front-end DAC.…”

Section: Introductionmentioning

confidence: 99%

Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer

Rajaee

Moon

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

Abstract-A new delta-sigma Analog-to-Digital Converter (ADC) is presented in this paper. A two-step pipeline ADC is used as the quantizer of this delta-sigma modulator to reduce the quantization noise at the output of the modulator. The proposed structure relaxes the output swing and gain requirements of the integrators. In addition, the front-end DAC of the proposed modulator is simplified. Simulation results verify the effectiveness of the proposed architecture.

show abstract

“…Many efforts have been investigated to reduce the power dissipation of the DSM by increasing complexity in hardware and in no. of quantization levels, such as non-uniform quantizer [8], two step quantizer [9]. Researchers also tried to reduce DEM complexity [10].…”

Section: Introductionmentioning

confidence: 99%

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

Gupta¹,

Gupta²,

Baghel³

2018

IJET

View full text Add to dashboard Cite

A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/√ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator's delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

show abstract

Multibit Delta-Sigma Modulator With Two-Step Quantization and Segmented DAC

Cited by 26 publications

References 7 publications

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

Contact Info

Product

Resources

About