The design of a mixed-signal random number generator (RNG) integrated circuit (IC) suitable for integration with hardware cryptographic systems is presented. Certain applications in cryptography require the use of a truly RNG, a device which produces unpredictable and unbiased digital signals derived from a fundamental noise mechanism. For IC-based cryptographic systems, an RNG must harness randomness from a low-power noise signal yet remain insensitive to deterministic influences such as crosstalk, power supply noise, and clock signal coupling through the substrate. An RNG IC utilizing established analog IC design techniques was designed and fabricated in a 2-m CMOS technology. Sequences generated by the experimental system repeatedly passed many standard randomness tests for bit rates up to 1.4 MHz. No changes in randomness performance were observed as the system was exposed to power supply noise and substrate signal coupling. The system occupies a total chip area of 1.5 mm 2 and dissipates 3.9 mW of power.Index Terms-Cryptography, noise generator, random bit generator, random number generator, truly random.

A 2.7-V sigma-delta modulator with a 6-bit quantizer is fabricated in a 0.18-m CMOS process. The modulator makes use of noise-shaped dynamic element matching (DEM) and quantizer offset chopping to attain high linearity over a wide bandwidth. The DEM algorithm is implemented in such a way as to minimize additional delay within the feedback loop of the modulator, thereby enabling the use of the highest resolution quantizer yet reported in a multibit sigma-delta analog-to-digital converter of this speed. The part achieves 95-dB peak spurious-free dynamic range and 77-dB signal-to-noise ratio over a 625-kHz bandwidth, and consumes 30 mW at a sampling frequency of 23 MHz. The part achieves 70-dB signal-to-noise ratio over a 1.92-MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.

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