A multibit sigma-delta ADC for multimode receivers

Miller, M.; Petrie, C.S.

doi:10.1109/jssc.2002.808321

Cited by 127 publications

(47 citation statements)

References 7 publications

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“…This strategy allows a simple and area-efficient design that does not require the use of switchable passives. However, as shown already in [7], this approach leads to poor power optimization and it is mostly avoided in state-of-the-art literature. Therefore, it will not be considered in the rest of this paper.…”

Section: Overview Of the Methodologymentioning

confidence: 99%

“…The difference is just 1μW in both MR/MB and LR/HB modes. As mentioned above, the C s,i in all the back-end integrators should ideally scale according to (7). However, as explained in Section III, the minimum size for C s,i is assumed in this work to be 50 fF to avoid that capacitor mismatch affects the ΔΣM performance.…”

Section: A Selection Of the Reconfigurable δσM Architecture For Tranmentioning

confidence: 99%

“…In this paper, FoM is calculated as in [6] is the effective number of bits and SNDR dB is the peak signal-to-noise-and-distortion ratio (in dB). ΔΣMs are good candidates for reconfigurability because of their inherent bandwidth resolution trade-off [7]. Reducing the oversampling lowers indeed P TOT , while decreasing the resulting ENOB.…”

Section: Introductionmentioning

confidence: 99%

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A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

Porrazzo

Morgado

Bello

et al. 2014

Circuit Theory & Apps

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SUMMARYThis paper presents a methodology to design reconfigurable switched-capacitor (SC) delta-sigma modulators Ms) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for lowbandwidth, medium-to-high resolution specifications, which are common in bio-medical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class-A and class-AB OTAs is presented. The power-optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution or program all sampling capacitors to the required resolution. The second approach results in the best trade-off between power efficiency and simplicity. A reconfigurable ΔΣM for bio-medical applications is designed at transistor-level in a 0.18μm CMOS process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%; validating thus the proposed approach.

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Section: Overview Of the Methodologymentioning

confidence: 99%

Section: A Selection Of the Reconfigurable δσM Architecture For Tranmentioning

confidence: 99%

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A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

Porrazzo

Morgado

Bello

et al. 2014

Circuit Theory & Apps

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“…Additional integrators, serving as usual noise shaping solutions, will be adopted in the feedback loop to attenuate the magnitude of the impulse response of the NTF at low frequencies (see e.g. (Miller and Petrie, 2003) for different Δ∑ modulator based MEMS gyroscope structures). This methodology is analogous to a PID (Proportional-Integral-Derivative) control system, in which the performance of the designed system depends on the experience of the designer (Datta, et al, 2000).…”

Section: δ∑ Modulator Based Mems Gyroscope 51mentioning

confidence: 99%

1-Bit processing based model predictive control for fractionated satellite missions

Bai

2014

Acta Astronautica

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In this thesis, a 1-bit processing based Model Predictive Control (OBMPC) structure is proposed for a fractionated satellite attitude control mission. Despite the appealing advantages of the MPC algorithm towards constrained MIMO control applications, implementing the MPC algorithm onboard a small satellite is certainly challenging due to the limited onboard resources. The proposed design is based on the 1-bit processing concept, which takes advantage of the affine relation between the 1-bit state feedback and multi-bit parameters to implement a multiplier free MPC controller.As multipliers are the major power consumer in online optimization, the OBMPC structure is proven to be more efficient in comparison to the conventional MPC implementation in term of power and circuit complexity. The system is in digital control nature, affected by quantization noise introduced by Δ∑ modulators. The stability issues and practical design criteria are also discussed in this work.Some other aspects are considered in this work to complete the control system. Firstly, the implementation of the OBMPC system relies on the 1-bit state feedbacks. Hence, 1-bit sensing components are needed to implement the OBMPC system. While the ∆∑ modulator based Microelectromechanical systems (MEMS) gyroscope is considered in this work, it is possible to implement this concept into other sensing components.Secondly, as the proposed attitude mission is based on the wireless inter-satellite link (ISL), a state estimator is required. However, conventional state estimators will once again introduce multi-bit signals, and compromise the simple, direct implementation of the OBMPC controller. Therefore, the 1-bit state estimator is also designed in this work to satisfy the requirements of the proposed fractionated attitude control mission.The simulation for the OBMPC is based on a 2U CubeSat model in a fractionated satellite structure, in which the payload and actuators are separated from the controller and controlled via the ISL. Matlab simulations and FPGA implementation based performance analysis shows that the OBMPC is feasible for fractionated satellite missions and is advantageous over the conventional MPC controllers. V VI

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“…Most high-speed modulators utilize data weighted averaging (DWA) to linearize their DAC [3]. Also, a well designed DWA only adds a shifter into the modulator loop; and the pointer update logic is done outside the loop [4]. A typical 4-bit barrel shifter in 0.18-m CMOS technology requires 0.9 ns.…”

Section: Input-feedforward Timing Issuesmentioning

confidence: 99%