On the implementation of input-feedforward delta-sigma modulators

Abstract

Abstract-This brief addresses some practical issues on the implementation of the input-feedforward delta-sigma modulators. First, the timing constraint imposed by the input-feedforward path is identified and a possible method to relax the constraint is proposed. Second, the drawbacks of the analog adder needed before the quantizer are explained and a method to eliminate the adder is proposed.

Design and simulation of a 3rd-order Discrete-Time Time-Interleaved delta-sigma modulator with shared integrators between two paths

“…The output of Q1 is called * ( ) in (13): * ( ) = ( ) − ( − 1) ( ) + ( ) (13) * ( ) approximates ( ) in the DTTI ΔΣ modulator. The error which is induced by this method is presented by equation (14). This error does not cause instability in the modulator but increases quantization noise of quantizer Q2 at the output ( ) followed by degrading the SNR of the modulator.…”

A 4th-Order Wideband Sigma Delta Modulator Using Linear System Theory Technique

“…If the DEM timing [11] is stringent, the mismatch can cause imperfect cancelling of signal component at the loop filter input and increase the linearity requirements of the modulator. Although the DEM timing and modulator input delay can be rightly controlled by clock signal in switched-capacitor △ ∑ ADCs, the insufficient speed of switched-capacitor can introduce gain error at the DAC feedback path and it should be avoided in actual realization.…”

A 4th-Order Low-distortion Low-pass Modulator Using Timing-Sharing Technique

“…It holds the unity signal transfer function (STF), greatly relax DEM issue and does not use an adder. It is learned that delay redistribution structure (DRD) and capacitive input feedforward (CIF) are two essential methods to achieve this topology [10]. Delay redistribution structure (DRD) is used to relax DEM timing.…”