No abstract

this paper presents a generalised new formula for impulse-invariant transformation which can be used to convert an nth-order Discrete-Time (DT) ΔΣ modulator to an nth-order equivalent Continuous-Time (CT) ΔΣ modulator. Impulse-invariant transformation formulas have been published in many open literature articles for s-domain to zdomain conversion and vice-versa. However, some of the published works contain omissions and oversights. To verify the newly derived formulas, very many designs of varying orders have been tested and a representative 4th-order singleloop DT ΔΣ modulator converted to an equivalent CT ΔΣ modulator through the new formulas are presented in this paper. The simulation results confirm that the CT ΔΣ modulator which has been derived by these formulas works in accordance with the initial DT specifications without any noticeable degradation in performance in comparison to its original DT ΔΣ modulator prototype.

This paper presents a 3rd-order two-path continuous-time time-interleaved (CTTI) delta-sigma modulator which is implemented in standard 90 nm CMOS technology. The architecture uses a novel method to resolve the delayless feedback path issue arising from the sharing of integrators between paths. By exploiting the concept of the time-interleaving techniques and through the use time domain equations, a conventional single path 3rd-order discrete-time (DT) DR modulator is converted into a corresponding two-path discrete-time time-interleaved (DTTI) counterpart. The equivalent CTTI version derived from the DTTI DR modulator by determining the DT loop filters and converting them to the equivalent continuous-time loop filters through the use of the Impulse Invariant Transformation. Sharing the integrators between two paths of the reported modulator makes it robust to path mismatch effects compared to the typical timeinterleaved modulators which have individual integrators in all paths. The modulator achieves a dynamic range of 12 bits with an OverSampling Ratio of 16 over a bandwidth of 10 MHz and dissipates only 28 mW of power from a 1.8-V supply. The clock frequency of the modulator is 320 MHz but integrators, quantizers and DACs operate at 160 MHz.

This paper describes a 10-bit I5OMSIs CMOS parallel pipeline ADC. The converter includes four parallel interleaved pipeline AID converters with analog background calibration using adaptive signal processing, an extra channel, and mixed signal integrators that match the. offsets and gains of time-interleaved ADC channels. With monolithic analog background calibration, the SNDR in all comer cases (SS, SF, FS, FF, and TT) and temperature between 4 0°C to 85°C is better than 57dB. The power consumption is ,120Omw at a 3.0V supply voltage. This work is achieved in a 0.6 p n CMOS process.

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