No abstract

This paper describes a 10-bit I5OMSIs CMOS parallel pipeline ADC. The converter includes four parallel interleaved pipeline AID converters with analog background calibration using adaptive signal processing, an extra channel, and mixed signal integrators that match the. offsets and gains of time-interleaved ADC channels. With monolithic analog background calibration, the SNDR in all comer cases (SS, SF, FS, FF, and TT) and temperature between 4 0°C to 85°C is better than 57dB. The power consumption is ,120Omw at a 3.0V supply voltage. This work is achieved in a 0.6 p n CMOS process.