Multichannel Time-to-Digital Converters With Automatic Calibration in Xilinx Zynq-7000 FPGA Devices

Low-Hardware Consumption, Resolution-Configurable Gray Code Oscillator Time-to-Digital Converters Implemented in 16 nm, 20 nm, and 28 nm FPGAs

“…Our previous work [44] presented a PS-based architecture to achieve automatic calibration. However, this design is devicedependent and its resolution is fixed.…”

“…With 𝑇 𝑣𝑖𝑟 and 𝑇 𝑟𝑎𝑤 , like the mixed calibration [32] and weighted calibration methods [44], the compensation factors can be calculated. However, both the mixed calibration method [32] and weighted calibration methods [44] have a limited compensation range, causing "missing bins" (highlighted in blue in Fig. 6a and Fig.…”

High-Resolution Time-to-Digital Converters (Tdcs) with a Bidirectional Encoder

“…Differently, for the falling-edge detection, the pattern detector identifies the pattern "000001", and the edge detector identifies the pattern "01". Then, similar to our previous work [27], we can convert four one-hot codes to four binary codes to generate the final code. Besides, Fig.…”

“…With the well-designed WU launcher, four logic transitions (two rising edges and two falling edges) are detectable in every sub-TDL. In our previous work (a TDC with two-edge WU A) [27], rising and falling edges in sub-TDLs' outputs are respectively detected and converted to one-hot code by positioning "0-1" and "1-0" patterns. Then every one-hot code is converted to the corresponding binary code for final result calculations.…”

A Novel Sobel Edge Detection Accelerator Based on Reconfigurable Architecture

“…In addition, in order to effectively implement edge detection, the algorithm becomes more and more complex, which is a huge challenge to the edge detection accelerator with reconfigurable architecture. Jiang et al [11][12][13][14][15] put forward sequence stream processor and pipeline processing method to build the edge detection accelerator based on reconfigurable architecture with the purpose of simplifying computing components and improving parallelism, and achieved certain results. However, these systems did not optimize the architecture for video streams, nor did they consider the parallel acceleration of memory in the reconfigurable architecture, but only achieved processing efficiency by improving the performance of computing components.…”