Multilanguage design of heterogeneous systems

Abstract

Multilanguage solutions are required for the design of heterogeneous systems where different parts belong to different application classes e.g. control/data or continuous/discrete. The main problem that needs to be solved when dealing with multilanguage design is the refinement of communication between heterogeneous subsystems. This paper discusses the basic concepts of multilanguage design and introduces MUSIC a Multilanguage design approach. The paper also shows the application of this approach in the case of a mechatronic system.

SystemC co-simulation for core-based embedded systems

“…Nevertheless they are adequate just in the very first stage of the development, before the HW/SW partitioning, because the HW and SW design flows need different techniques and different tools when the abstraction level decreases toward a real implementation. [3][4][5][6] use distinct simulation engines and different language descriptions for the hardware and the software side. This allows to use levels of abstraction lower than the behavioral one, and to evaluate the software in its compiled (binary code) form.…”

A Smooth Refinement Flow for Co-designing HW and SW Threads

“…Co-design flows start generally at system level, where the embedded system is described by a set of untimed functional processes communicating by means of high-level transactions. Then, after functional validation, HW/SW partitioning takes place and HW/SW co-simulation strategies are adopted to allow the co-verification of the partitioned system [4,6,8,9,10]. Early co-simulation approaches require to set up complex heterogenous environments where HW and SW parts are executed by using different simulators [8,9].…”

“…Then, after functional validation, HW/SW partitioning takes place and HW/SW co-simulation strategies are adopted to allow the co-verification of the partitioned system [4,6,8,9,10]. Early co-simulation approaches require to set up complex heterogenous environments where HW and SW parts are executed by using different simulators [8,9]. This heterogeneous style is sub-optimal in terms of simulation performance and easiness of integration, but it was the only possible choice when VHDL or Verilog simulation was the highest possible level of abstraction for HW simulation.…”

Validation in a component-based design flow for multicore SoCs

“…al. presents a tool called MCI that enables multilanguage cosimulation [18]. These solutions are very efficient for multi-language simulation, but they don't treat in a systematic way the multi-level cosimulation.…”